prithvi_sinha's projects

Verilog Code
11 months ago
Y is 1 when A(MSB),B,C,D(LSB) = 0,1,4,5,10,11,14 else Y is 0.
11 months ago
Y is 1 when A (MSB),B,C,D (LSB) = 1,2,4,5,6,7,8,9,11,12,13 else Y is 0
11 months ago
Y = 1, if A(MSB), B, C, D(LSB) – are 0,2,8,10,12,13,14,15, and else Y=0
11 months ago
(A + B)(C + D)
11 months ago
(A+B)C
11 months ago
(A+B)C and (A+B)(C+D)
11 months ago
AB
11 months ago
AB+C
11 months ago
Complex Prime Number Detection
11 months ago
Simplified Prime Number Detection
11 months ago
Multiple Slide Switch
11 months ago
Dip Switch And LED
11 months ago
Slide Switch and LED
11 months ago
Push Button and LED By Prithvi Sinha
11 months ago