/**
 * Project Direct Ghost
 * ====================
 * A small test design for "TinyTapeout".
 *
 * The design contains an 8-bit Linear Feedback Shift Register
 * (LFSR) and full adder.
 *
 * Inputs:
 *  - IN0: Clock
 *  - IN1: Alternate feed enable for LFSR (active high)
 *  - IN2: Alternate feed data for LFSR (for seeding D-flip flops)
 *  - IN3: A_in for Full Adder
 *  - IN4: B_in for Full Adder
 *  - IN5: C_in for Full Adder
 *  - IN6-7: Unused
 *
 * Outputs:
 *  - OUT0: Output of LFSR
 *  - OUT1: Q for Full Adder
 *  - OUT2: C_out for Full Adder
 *  - OUT3-7: Unused
 *
 * LFSR
 * ====
 * The LFSR is a maximal LFSR based on the polynomial:
 *
 *   x^8 + x^6 + x^5 + x^3 + 1
 *
 * It is an illegal state for the D-Flip Flops to be all 0. While
 * the flip flops should initialize to a random state in the real
 * design, this cannot be guaranteed. As a workaround, there is a
 * multiplexer at the input, that will allow you to "seed" the
 * register state.
 *
 * To seed the register state, enable the alternate input by putting
 * IN1 to logic high. Place a value on IN2, and pulse the clock by
 * clicking "Step". Continue to do this until the register is in a
 * state you like.
 *
 * After the register is seeded. disable the alternate input by putting
 * IN1 to logic low. Every time "Step" is clicked, a new value from the
 * LFSR will output on OUT0.
 *
 * https://en.wikipedia.org/wiki/Linear-feedback_shift_register
 *
 * Full Adder
 * ==========
 * The full adder is a classic design, used as a part of an arithmatic
 * logic unit (ALU). There are two bits that come in, and a single bit
 * comes out. The inputs A and B will sum on the output Q.
 *
 * However, in order to be more useful, more bits are required.
 * Therefore, the logic supports a "carry in" and "carry out" bit,
 * designed to be fed into the next part of the adder.
 *
 * For the sake of the design, the inputs and outputs are clocked.
 *
 * Logic Table
 * ------------
 *
 * |  A  |  B  |  C_in  |  Q  |  Q_out  |
 * |-----|-----|--------|-----|---------|
 * |  0  |  0  |   0    |  0  |    0    |
 * |  1  |  0  |   0    |  1  |    0    |
 * |  0  |  1  |   0    |  1  |    0    |
 * |  1  |  1  |   0    |  0  |    1    |
 * |  0  |  0  |   1    |  1  |    0    |
 * |  1  |  0  |   1    |  0  |    1    |
 * |  0  |  1  |   1    |  0  |    1    |
 * |  1  |  1  |   1    |  1  |    1    |
 */
void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
10k
clock1:CLK
pwr2:GND
pwr1:VCC
Digital InputBreakout
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN7
chip1:IN6
chip1:IN5
chip1:IN4
chip1:IN3
chip1:IN2
chip1:IN1
chip1:IN0
Digital OutputBreakout
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT7
chip2:EXTOUT6
chip2:EXTOUT5
chip2:EXTOUT4
chip2:EXTOUT3
chip2:EXTOUT2
chip2:EXTOUT1
chip2:EXTOUT0
sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
gate3:A
gate3:B
gate3:OUT
gate100:A
gate100:B
gate100:OUT
mux1:A
mux1:B
mux1:SEL
mux1:OUT
flipflop1:D
flipflop1:CLK
flipflop1:Q
flipflop1:NOTQ
gate7:A
gate7:B
gate7:OUT
gate9:A
gate9:B
gate9:OUT
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
flipflop3:D
flipflop3:CLK
flipflop3:Q
flipflop3:NOTQ
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
flipflop5:D
flipflop5:CLK
flipflop5:Q
flipflop5:NOTQ
flipflop6:D
flipflop6:CLK
flipflop6:Q
flipflop6:NOTQ
flipflop7:D
flipflop7:CLK
flipflop7:Q
flipflop7:NOTQ
flipflop8:D
flipflop8:CLK
flipflop8:Q
flipflop8:NOTQ
gate10:A
gate10:B
gate10:OUT
gate11:A
gate11:B
gate11:OUT
flipflop9:D
flipflop9:CLK
flipflop9:Q
flipflop9:NOTQ
flipflop10:D
flipflop10:CLK
flipflop10:Q
flipflop10:NOTQ
flipflop11:D
flipflop11:CLK
flipflop11:Q
flipflop11:NOTQ
flipflop12:D
flipflop12:CLK
flipflop12:Q
flipflop12:NOTQ
flipflop13:D
flipflop13:CLK
flipflop13:Q
flipflop13:NOTQ
gate1:A
gate1:B
gate1:OUT
gate2:A
gate2:B
gate2:OUT

ERC Warnings

flipflop10:CLK: Clock driven by combinatorial logic
flipflop11:CLK: Clock driven by combinatorial logic
flipflop12:CLK: Clock driven by combinatorial logic
flipflop13:CLK: Clock driven by combinatorial logic
flipflop1:CLK: Clock driven by combinatorial logic
flipflop2:CLK: Clock driven by combinatorial logic
flipflop3:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop5:CLK: Clock driven by combinatorial logic
flipflop6:CLK: Clock driven by combinatorial logic
3 additional warning(s) hidden