// Inputs
// 1 - CLK
// 2 - COUNTER ENABLE (active high)
// 3 - DATA INPUT
// 4 - LOOP ENABLE (active high)
// 5 - COUNTER RESET (active low/syncronous reset)
// set pin 2 low, pin 4 low, pin 5 low, pulse clock on pin 1
// clock in 64 bits using using pin 1 for clock pin 3 for data
// set pin 2 high, pin 4 high, pin 5 high
// enable clock on pin 1 and watch the 64 bit pattern loaded display out the outputs in 8 bit chunks
void setup() {
// put your setup code here, to run once:
}
void loop() {
// put your main code here, to run repeatedly:
}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
clock1:CLK
pwr2:GND
pwr1:VCC
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN7
chip1:IN6
chip1:IN5
chip1:IN4
chip1:IN3
chip1:IN2
chip1:IN1
chip1:IN0
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT7
chip2:EXTOUT6
chip2:EXTOUT5
chip2:EXTOUT4
chip2:EXTOUT3
chip2:EXTOUT2
chip2:EXTOUT1
chip2:EXTOUT0
sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
gate2:A
gate2:B
gate2:OUT
gate3:A
gate3:B
gate3:OUT
gate4:A
gate4:B
gate4:OUT
gate5:IN
gate5:OUT
gate6:IN
gate6:OUT
mux1:A
mux1:B
mux1:SEL
mux1:OUT
flipflop1:D
flipflop1:CLK
flipflop1:Q
flipflop1:NOTQ
pwr4:VCC
pwr5:GND
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
flipflop3:D
flipflop3:CLK
flipflop3:Q
flipflop3:NOTQ
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
flipflop5:D
flipflop5:CLK
flipflop5:Q
flipflop5:NOTQ
flipflop6:D
flipflop6:CLK
flipflop6:Q
flipflop6:NOTQ
flipflop7:D
flipflop7:CLK
flipflop7:Q
flipflop7:NOTQ
flipflop8:D
flipflop8:CLK
flipflop8:Q
flipflop8:NOTQ
flipflop9:D
flipflop9:CLK
flipflop9:Q
flipflop9:NOTQ
pwr6:VCC
led1:A
led1:C
pwr7:VCC
led2:A
led2:C
pwr8:VCC
led3:A
led3:C
pwr9:VCC
led4:A
led4:C
pwr10:VCC
led5:A
led5:C
pwr11:VCC
led6:A
led6:C
pwr12:VCC
led7:A
led7:C
pwr13:VCC
led8:A
led8:C
flipflop10:D
flipflop10:CLK
flipflop10:Q
flipflop10:NOTQ
flipflop11:D
flipflop11:CLK
flipflop11:Q
flipflop11:NOTQ
flipflop12:D
flipflop12:CLK
flipflop12:Q
flipflop12:NOTQ
pwr14:VCC
led9:A
led9:C
pwr15:VCC
led10:A
led10:C
pwr16:VCC
led11:A
led11:C
gate7:A
gate7:B
gate7:OUT
gate8:A
gate8:B
gate8:OUT
gate9:A
gate9:B
gate9:OUT
gate10:A
gate10:B
gate10:OUT
gate11:A
gate11:B
gate11:OUT
gate16:A
gate16:B
gate16:OUT
flipflop14:D
flipflop14:CLK
flipflop14:Q
flipflop14:NOTQ
flipflop15:D
flipflop15:CLK
flipflop15:Q
flipflop15:NOTQ
flipflop16:D
flipflop16:CLK
flipflop16:Q
flipflop16:NOTQ
flipflop17:D
flipflop17:CLK
flipflop17:Q
flipflop17:NOTQ
flipflop18:D
flipflop18:CLK
flipflop18:Q
flipflop18:NOTQ
flipflop19:D
flipflop19:CLK
flipflop19:Q
flipflop19:NOTQ
flipflop20:D
flipflop20:CLK
flipflop20:Q
flipflop20:NOTQ
flipflop21:D
flipflop21:CLK
flipflop21:Q
flipflop21:NOTQ
flipflop22:D
flipflop22:CLK
flipflop22:Q
flipflop22:NOTQ
flipflop23:D
flipflop23:CLK
flipflop23:Q
flipflop23:NOTQ
flipflop24:D
flipflop24:CLK
flipflop24:Q
flipflop24:NOTQ
flipflop25:D
flipflop25:CLK
flipflop25:Q
flipflop25:NOTQ
flipflop26:D
flipflop26:CLK
flipflop26:Q
flipflop26:NOTQ
flipflop27:D
flipflop27:CLK
flipflop27:Q
flipflop27:NOTQ
flipflop28:D
flipflop28:CLK
flipflop28:Q
flipflop28:NOTQ
flipflop29:D
flipflop29:CLK
flipflop29:Q
flipflop29:NOTQ
flipflop30:D
flipflop30:CLK
flipflop30:Q
flipflop30:NOTQ
flipflop31:D
flipflop31:CLK
flipflop31:Q
flipflop31:NOTQ
flipflop32:D
flipflop32:CLK
flipflop32:Q
flipflop32:NOTQ
flipflop33:D
flipflop33:CLK
flipflop33:Q
flipflop33:NOTQ
flipflop34:D
flipflop34:CLK
flipflop34:Q
flipflop34:NOTQ
flipflop35:D
flipflop35:CLK
flipflop35:Q
flipflop35:NOTQ
flipflop36:D
flipflop36:CLK
flipflop36:Q
flipflop36:NOTQ
flipflop37:D
flipflop37:CLK
flipflop37:Q
flipflop37:NOTQ
flipflop38:D
flipflop38:CLK
flipflop38:Q
flipflop38:NOTQ
flipflop39:D
flipflop39:CLK
flipflop39:Q
flipflop39:NOTQ
flipflop40:D
flipflop40:CLK
flipflop40:Q
flipflop40:NOTQ
flipflop41:D
flipflop41:CLK
flipflop41:Q
flipflop41:NOTQ
flipflop42:D
flipflop42:CLK
flipflop42:Q
flipflop42:NOTQ
flipflop43:D
flipflop43:CLK
flipflop43:Q
flipflop43:NOTQ
flipflop44:D
flipflop44:CLK
flipflop44:Q
flipflop44:NOTQ
flipflop45:D
flipflop45:CLK
flipflop45:Q
flipflop45:NOTQ
flipflop46:D
flipflop46:CLK
flipflop46:Q
flipflop46:NOTQ
flipflop47:D
flipflop47:CLK
flipflop47:Q
flipflop47:NOTQ
flipflop48:D
flipflop48:CLK
flipflop48:Q
flipflop48:NOTQ
flipflop49:D
flipflop49:CLK
flipflop49:Q
flipflop49:NOTQ
flipflop50:D
flipflop50:CLK
flipflop50:Q
flipflop50:NOTQ
flipflop51:D
flipflop51:CLK
flipflop51:Q
flipflop51:NOTQ
flipflop52:D
flipflop52:CLK
flipflop52:Q
flipflop52:NOTQ
flipflop53:D
flipflop53:CLK
flipflop53:Q
flipflop53:NOTQ
flipflop54:D
flipflop54:CLK
flipflop54:Q
flipflop54:NOTQ
flipflop55:D
flipflop55:CLK
flipflop55:Q
flipflop55:NOTQ
flipflop56:D
flipflop56:CLK
flipflop56:Q
flipflop56:NOTQ
flipflop57:D
flipflop57:CLK
flipflop57:Q
flipflop57:NOTQ
flipflop58:D
flipflop58:CLK
flipflop58:Q
flipflop58:NOTQ
flipflop59:D
flipflop59:CLK
flipflop59:Q
flipflop59:NOTQ
flipflop60:D
flipflop60:CLK
flipflop60:Q
flipflop60:NOTQ
flipflop61:D
flipflop61:CLK
flipflop61:Q
flipflop61:NOTQ
flipflop62:D
flipflop62:CLK
flipflop62:Q
flipflop62:NOTQ
flipflop63:D
flipflop63:CLK
flipflop63:Q
flipflop63:NOTQ
flipflop64:D
flipflop64:CLK
flipflop64:Q
flipflop64:NOTQ
flipflop65:D
flipflop65:CLK
flipflop65:Q
flipflop65:NOTQ
flipflop66:D
flipflop66:CLK
flipflop66:Q
flipflop66:NOTQ
flipflop67:D
flipflop67:CLK
flipflop67:Q
flipflop67:NOTQ
flipflop68:D
flipflop68:CLK
flipflop68:Q
flipflop68:NOTQ
flipflop69:D
flipflop69:CLK
flipflop69:Q
flipflop69:NOTQ
flipflop70:D
flipflop70:CLK
flipflop70:Q
flipflop70:NOTQ
flipflop71:D
flipflop71:CLK
flipflop71:Q
flipflop71:NOTQ
flipflop72:D
flipflop72:CLK
flipflop72:Q
flipflop72:NOTQ
flipflop73:D
flipflop73:CLK
flipflop73:Q
flipflop73:NOTQ
flipflop74:D
flipflop74:CLK
flipflop74:Q
flipflop74:NOTQ
flipflop75:D
flipflop75:CLK
flipflop75:Q
flipflop75:NOTQ
flipflop76:D
flipflop76:CLK
flipflop76:Q
flipflop76:NOTQ
flipflop77:D
flipflop77:CLK
flipflop77:Q
flipflop77:NOTQ
gate1:A
gate1:B
gate1:OUT
gate14:A
gate14:B
gate14:OUT
gate15:A
gate15:B
gate15:OUT
pwr17:VCC
mux2:A
mux2:B
mux2:SEL
mux2:OUT
gate12:A
gate12:B
gate12:OUT
gate13:A
gate13:B
gate13:OUT
gate17:A
gate17:B
gate17:OUT
ERC Warnings
flipflop1:CLK: Clock driven by combinatorial logic
flipflop2:CLK: Clock driven by combinatorial logic
flipflop3:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop5:CLK: Clock driven by combinatorial logic
flipflop6:CLK: Clock driven by combinatorial logic
flipflop7:CLK: Clock driven by combinatorial logic
flipflop8:CLK: Clock driven by combinatorial logic
flipflop10:CLK: Clock driven by combinatorial logic
flipflop11:CLK: Clock driven by combinatorial logic
65 additional warning(s) hidden