void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
10k
clock1:CLK
sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
pwr2:GND
pwr1:VCC
Digital InputBreakout
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN7
chip1:IN6
chip1:IN5
chip1:IN4
chip1:IN3
chip1:IN2
chip1:IN1
chip1:IN0
Digital OutputBreakout
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT7
chip2:EXTOUT6
chip2:EXTOUT5
chip2:EXTOUT4
chip2:EXTOUT3
chip2:EXTOUT2
chip2:EXTOUT1
chip2:EXTOUT0
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
bargraph1:A1
bargraph1:A2
bargraph1:A3
bargraph1:A4
bargraph1:A5
bargraph1:A6
bargraph1:A7
bargraph1:A8
bargraph1:A9
bargraph1:A10
bargraph1:C1
bargraph1:C2
bargraph1:C3
bargraph1:C4
bargraph1:C5
bargraph1:C6
bargraph1:C7
bargraph1:C8
bargraph1:C9
bargraph1:C10
gate7:IN
gate7:OUT
flipflop3:D
flipflop3:CLK
flipflop3:Q
flipflop3:NOTQ
gate8:A
gate8:B
gate8:OUT
mux2:A
mux2:B
mux2:SEL
mux2:OUT
gate12:A
gate12:B
gate12:OUT
INPUT ------- clk[0] en[1] load[2] countDown[3] dataIn[4:7]
OUTPUT ------- countOut [0:3]
This IP block simulates a binary synchronous (parallel) MOD-16 counter. Applications are CPU's, PWM signal generators, etc. It features: - tri-direction (pause, count up, count down) - loadable (use data[3:1], eg. for jump instruction) - synchronous output(at rising edge) with async (ripple) setup of next count) - easy to control, fast and scalable (each 1 bit counter only depends on previous counter)
gate10:A
gate10:B
gate10:OUT
gate11:A
gate11:B
gate11:OUT
gate13:A
gate13:B
gate13:OUT
led4:A
led4:C
pwr6:GND
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
gate15:A
gate15:B
gate15:OUT
mux3:A
mux3:B
mux3:SEL
mux3:OUT
gate16:A
gate16:B
gate16:OUT
gate17:A
gate17:B
gate17:OUT
gate18:A
gate18:B
gate18:OUT
gate19:A
gate19:B
gate19:OUT
LEGEND yellow = clock signal purple = count signal teal = load signal red = data signals white = count up signal grey = count down signal
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
gate14:A
gate14:B
gate14:OUT
mux4:A
mux4:B
mux4:SEL
mux4:OUT
gate20:A
gate20:B
gate20:OUT
gate21:A
gate21:B
gate21:OUT
gate22:A
gate22:B
gate22:OUT
gate23:A
gate23:B
gate23:OUT
flipflop5:D
flipflop5:CLK
flipflop5:Q
flipflop5:NOTQ
gate24:A
gate24:B
gate24:OUT
mux5:A
mux5:B
mux5:SEL
mux5:OUT

ERC Warnings

flipflop2:CLK: Clock driven by combinatorial logic
flipflop3:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop5:CLK: Clock driven by combinatorial logic