void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
10k
clock1:CLK
pwr1:VCC
Digital InputBreakout
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN7
chip1:IN6
chip1:IN5
chip1:IN4
chip1:IN3
chip1:IN2
chip1:IN1
chip1:IN0
Digital OutputBreakout
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT7
chip2:EXTOUT6
chip2:EXTOUT5
chip2:EXTOUT4
chip2:EXTOUT3
chip2:EXTOUT2
chip2:EXTOUT1
chip2:EXTOUT0
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
gate1:A
gate1:B
gate1:OUT
gate2:A
gate2:B
gate2:OUT
gate3:A
gate3:B
gate3:OUT
gate4:A
gate4:B
gate4:OUT
gate5:IN
gate5:OUT
gate6:IN
gate6:OUT
mux1:A
mux1:B
mux1:SEL
mux1:OUT
flipflop1:D
flipflop1:CLK
flipflop1:Q
flipflop1:NOTQ
pwr4:VCC
pwr5:GND
gate7:A
gate7:B
gate7:OUT
gate8:A
gate8:B
gate8:OUT
gate164:IN
gate164:OUT
gate165:IN
gate165:OUT
gate166:IN
gate166:OUT
gate167:IN
gate167:OUT
gate168:IN
gate168:OUT
gate169:IN
gate169:OUT
gate170:IN
gate170:OUT
pwr22:GND
pwr23:GND
pwr24:GND
pwr25:GND
pwr26:GND
pwr27:GND
pwr28:GND
gate183:IN
gate183:OUT
gate195:IN
gate195:OUT
gate184:A
gate184:B
gate184:OUT
led1:A
led1:C
r1:1
r1:2
pwr8:GND
r2:1
r2:2
pwr9:GND
r4:1
r4:2
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
mux2:A
mux2:B
mux2:SEL
mux2:OUT
led3:A
led3:C
pwr2:GND
mux5:A
mux5:B
mux5:SEL
mux5:OUT
gate9:IN
gate9:OUT
gate10:IN
gate10:OUT
mux3:A
mux3:B
mux3:SEL
mux3:OUT
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
led4:A
led4:C
pwr12:GND
mux4:A
mux4:B
mux4:SEL
mux4:OUT
gate12:IN
gate12:OUT
gate13:IN
gate13:OUT
mux6:A
mux6:B
mux6:SEL
mux6:OUT
flipflop6:D
flipflop6:CLK
flipflop6:Q
flipflop6:NOTQ
led5:A
led5:C
pwr14:GND
mux7:A
mux7:B
mux7:SEL
mux7:OUT
gate15:IN
gate15:OUT
gate16:IN
gate16:OUT
mux8:A
mux8:B
mux8:SEL
mux8:OUT
flipflop8:D
flipflop8:CLK
flipflop8:Q
flipflop8:NOTQ
led6:A
led6:C
pwr16:GND
mux9:A
mux9:B
mux9:SEL
mux9:OUT
gate18:IN
gate18:OUT
gate19:IN
gate19:OUT
mux10:A
mux10:B
mux10:SEL
mux10:OUT
flipflop10:D
flipflop10:CLK
flipflop10:Q
flipflop10:NOTQ
led7:A
led7:C
pwr18:GND
mux11:A
mux11:B
mux11:SEL
mux11:OUT
gate21:IN
gate21:OUT
gate23:IN
gate23:OUT
mux12:A
mux12:B
mux12:SEL
mux12:OUT
flipflop12:D
flipflop12:CLK
flipflop12:Q
flipflop12:NOTQ
led8:A
led8:C
pwr20:GND
mux13:A
mux13:B
mux13:SEL
mux13:OUT
gate25:IN
gate25:OUT
gate26:IN
gate26:OUT
mux14:A
mux14:B
mux14:SEL
mux14:OUT
flipflop14:D
flipflop14:CLK
flipflop14:Q
flipflop14:NOTQ
led9:A
led9:C
pwr29:GND
mux15:A
mux15:B
mux15:SEL
mux15:OUT
gate28:IN
gate28:OUT
gate29:IN
gate29:OUT
mux16:A
mux16:B
mux16:SEL
mux16:OUT
flipflop16:D
flipflop16:CLK
flipflop16:Q
flipflop16:NOTQ
led10:A
led10:C
pwr31:GND
mux17:A
mux17:B
mux17:SEL
mux17:OUT
gate31:IN
gate31:OUT
gate32:IN
gate32:OUT
mux18:A
mux18:B
mux18:SEL
mux18:OUT
flipflop18:D
flipflop18:CLK
flipflop18:Q
flipflop18:NOTQ
led11:A
led11:C
pwr33:GND
mux19:A
mux19:B
mux19:SEL
mux19:OUT
gate34:IN
gate34:OUT
gate35:IN
gate35:OUT
mux20:A
mux20:B
mux20:SEL
mux20:OUT
flipflop20:D
flipflop20:CLK
flipflop20:Q
flipflop20:NOTQ
led12:A
led12:C
pwr35:GND
mux21:A
mux21:B
mux21:SEL
mux21:OUT
gate37:IN
gate37:OUT
gate38:IN
gate38:OUT
gate11:IN
gate11:OUT
gate14:IN
gate14:OUT
gate17:IN
gate17:OUT
gate20:IN
gate20:OUT
gate30:IN
gate30:OUT
gate33:IN
gate33:OUT
gate36:IN
gate36:OUT
gate24:IN
gate24:OUT
gate27:IN
gate27:OUT
gate39:IN
gate39:OUT
gate40:IN
gate40:OUT
gate41:IN
gate41:OUT
gate42:IN
gate42:OUT
gate43:IN
gate43:OUT
gate44:IN
gate44:OUT
gate45:IN
gate45:OUT
r6:1
r6:2
pwr11:GND
pwr39:GND
r7:1
r7:2
pwr40:GND
pwr41:GND
pwr13:VCC
pwr15:VCC
pwr17:VCC
pwr19:VCC
pwr21:VCC
pwr30:VCC
pwr32:VCC
pwr34:VCC
pwr36:VCC
gate46:A
gate46:B
gate46:OUT
gate47:IN
gate47:OUT
gate48:A
gate48:B
gate48:OUT
gate49:IN
gate49:OUT
gate50:A
gate50:B
gate50:OUT
gate51:IN
gate51:OUT
gate52:A
gate52:B
gate52:OUT
gate53:IN
gate53:OUT
gate54:A
gate54:B
gate54:OUT
gate55:IN
gate55:OUT
gate56:A
gate56:B
gate56:OUT
gate57:IN
gate57:OUT
gate58:A
gate58:B
gate58:OUT
gate59:IN
gate59:OUT
gate60:A
gate60:B
gate60:OUT
gate61:IN
gate61:OUT
gate62:A
gate62:B
gate62:OUT
gate63:IN
gate63:OUT
gate64:A
gate64:B
gate64:OUT
gate65:IN
gate65:OUT
gate66:A
gate66:B
gate66:OUT
gate67:A
gate67:B
gate67:OUT
gate68:A
gate68:B
gate68:OUT
gate70:A
gate70:B
gate70:OUT
gate71:A
gate71:B
gate71:OUT
gate72:A
gate72:B
gate72:OUT
gate74:A
gate74:B
gate74:OUT
gate76:A
gate76:B
gate76:OUT
gate79:A
gate79:B
gate79:OUT
pwr6:GND
pwr42:GND
pwr43:GND
pwr44:VCC
pwr45:GND
pwr46:VCC
pwr47:VCC
pwr48:VCC
pwr49:VCC
pwr50:VCC
gate69:IN
gate69:OUT
gate73:IN
gate73:OUT
gate75:A
gate75:B
gate75:OUT
gate77:A
gate77:B
gate77:OUT
D0D1D2D3D4D5D6D7GNDLOGIC
logic1:D0
logic1:D1
logic1:D2
logic1:D3
logic1:D4
logic1:D5
logic1:D6
logic1:D7
logic1:GND
pwr10:GND

ERC Warnings

flipflop2:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop6:CLK: Clock driven by combinatorial logic
flipflop8:CLK: Clock driven by combinatorial logic
flipflop10:CLK: Clock driven by combinatorial logic
flipflop12:CLK: Clock driven by combinatorial logic
flipflop14:CLK: Clock driven by combinatorial logic
flipflop16:CLK: Clock driven by combinatorial logic
flipflop18:CLK: Clock driven by combinatorial logic
flipflop20:CLK: Clock driven by combinatorial logic