void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
10k
clock1:CLK
pwr2:GND
pwr1:VCC
Digital InputBreakout
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN7
chip1:IN6
chip1:IN5
chip1:IN4
chip1:IN3
chip1:IN2
chip1:IN1
chip1:IN0
Digital OutputBreakout
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT7
chip2:EXTOUT6
chip2:EXTOUT5
chip2:EXTOUT4
chip2:EXTOUT3
chip2:EXTOUT2
chip2:EXTOUT1
chip2:EXTOUT0
sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
gate1:A
gate1:B
gate1:OUT
gate3:A
gate3:B
gate3:OUT
gate4:A
gate4:B
gate4:OUT
gate5:IN
gate5:OUT
gate6:IN
gate6:OUT
mux1:A
mux1:B
mux1:SEL
mux1:OUT
flipflop1:D
flipflop1:CLK
flipflop1:Q
flipflop1:NOTQ
pwr4:VCC
pwr5:GND
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
flipflop3:D
flipflop3:CLK
flipflop3:Q
flipflop3:NOTQ
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
flipflop5:D
flipflop5:CLK
flipflop5:Q
flipflop5:NOTQ
flipflop6:D
flipflop6:CLK
flipflop6:Q
flipflop6:NOTQ
flipflop7:D
flipflop7:CLK
flipflop7:Q
flipflop7:NOTQ
flipflop8:D
flipflop8:CLK
flipflop8:Q
flipflop8:NOTQ
gate7:A
gate7:B
gate7:OUT
flipflop9:D
flipflop9:CLK
flipflop9:Q
flipflop9:NOTQ
flipflop10:D
flipflop10:CLK
flipflop10:Q
flipflop10:NOTQ
flipflop11:D
flipflop11:CLK
flipflop11:Q
flipflop11:NOTQ
gate8:IN
gate8:OUT
gate9:A
gate9:B
gate9:OUT
gate10:A
gate10:B
gate10:OUT
gate11:A
gate11:B
gate11:OUT
gate14:A
gate14:B
gate14:OUT
mux2:A
mux2:B
mux2:SEL
mux2:OUT
mux3:A
mux3:B
mux3:SEL
mux3:OUT
mux4:A
mux4:B
mux4:SEL
mux4:OUT
mux5:A
mux5:B
mux5:SEL
mux5:OUT
mux6:A
mux6:B
mux6:SEL
mux6:OUT
mux7:A
mux7:B
mux7:SEL
mux7:OUT
mux8:A
mux8:B
mux8:SEL
mux8:OUT
mux9:A
mux9:B
mux9:SEL
mux9:OUT
mux10:A
mux10:B
mux10:SEL
mux10:OUT
mux11:A
mux11:B
mux11:SEL
mux11:OUT
mux12:A
mux12:B
mux12:SEL
mux12:OUT
mux13:A
mux13:B
mux13:SEL
mux13:OUT
mux14:A
mux14:B
mux14:SEL
mux14:OUT
mux15:A
mux15:B
mux15:SEL
mux15:OUT
mux16:A
mux16:B
mux16:SEL
mux16:OUT
gate18:IN
gate18:OUT
gate19:IN
gate19:OUT
gate20:IN
gate20:OUT
gate21:A
gate21:B
gate21:OUT
gate22:A
gate22:B
gate22:OUT
gate23:IN
gate23:OUT
gate24:A
gate24:B
gate24:OUT
gate25:A
gate25:B
gate25:OUT
gate26:A
gate26:B
gate26:OUT
gate27:IN
gate27:OUT
gate28:IN
gate28:OUT
mux22:A
mux22:B
mux22:SEL
mux22:OUT
mux23:A
mux23:B
mux23:SEL
mux23:OUT
mux24:A
mux24:B
mux24:SEL
mux24:OUT
mux25:A
mux25:B
mux25:SEL
mux25:OUT
mux26:A
mux26:B
mux26:SEL
mux26:OUT
gate29:IN
gate29:OUT
gate30:IN
gate30:OUT
gate31:IN
gate31:OUT
flipflop12:D
flipflop12:CLK
flipflop12:Q
flipflop12:NOTQ
flipflop13:D
flipflop13:CLK
flipflop13:Q
flipflop13:NOTQ
flipflop14:D
flipflop14:CLK
flipflop14:Q
flipflop14:NOTQ
flipflop15:D
flipflop15:CLK
flipflop15:Q
flipflop15:NOTQ
flipflop16:D
flipflop16:CLK
flipflop16:Q
flipflop16:NOTQ
flipflop17:D
flipflop17:CLK
flipflop17:Q
flipflop17:NOTQ
gate32:A
gate32:B
gate32:OUT
gate33:A
gate33:B
gate33:OUT
gate34:A
gate34:B
gate34:OUT
gate35:A
gate35:B
gate35:OUT
gate36:A
gate36:B
gate36:OUT
gate37:A
gate37:B
gate37:OUT
gate38:A
gate38:B
gate38:OUT
gate39:A
gate39:B
gate39:OUT
gate40:A
gate40:B
gate40:OUT
gate41:A
gate41:B
gate41:OUT
gate42:A
gate42:B
gate42:OUT
gate43:A
gate43:B
gate43:OUT

ERC Warnings

flipflop12:CLK: Clock driven by combinatorial logic
flipflop13:CLK: Clock driven by combinatorial logic
flipflop14:CLK: Clock driven by combinatorial logic
flipflop15:CLK: Clock driven by combinatorial logic
flipflop16:CLK: Clock driven by combinatorial logic
flipflop17:CLK: Clock driven by combinatorial logic
flipflop2:CLK: Clock driven by combinatorial logic
flipflop3:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop5:CLK: Clock driven by combinatorial logic
20 additional warning(s) hidden