void setup() {
// put your setup code here, to run once:
}
void loop() {
// put your main code here, to run repeatedly:
}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
clock1:CLK
pwr2:GND
pwr1:VCC
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN7
chip1:IN6
chip1:IN5
chip1:IN4
chip1:IN3
chip1:IN2
chip1:IN1
chip1:IN0
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT7
chip2:EXTOUT6
chip2:EXTOUT5
chip2:EXTOUT4
chip2:EXTOUT3
chip2:EXTOUT2
chip2:EXTOUT1
chip2:EXTOUT0
sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
gate1:A
gate1:B
gate1:OUT
gate2:A
gate2:B
gate2:OUT
gate3:A
gate3:B
gate3:OUT
gate4:A
gate4:B
gate4:OUT
gate5:IN
gate5:OUT
gate6:IN
gate6:OUT
mux1:A
mux1:B
mux1:SEL
mux1:OUT
pwr4:VCC
pwr5:GND
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
mux3:A
mux3:B
mux3:SEL
mux3:OUT
pwr7:VCC
flipflop3:D
flipflop3:CLK
flipflop3:Q
flipflop3:NOTQ
mux4:A
mux4:B
mux4:SEL
mux4:OUT
pwr8:VCC
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
mux5:A
mux5:B
mux5:SEL
mux5:OUT
pwr9:GND
flipflop5:D
flipflop5:CLK
flipflop5:Q
flipflop5:NOTQ
mux6:A
mux6:B
mux6:SEL
mux6:OUT
flipflop6:D
flipflop6:CLK
flipflop6:Q
flipflop6:NOTQ
mux7:A
mux7:B
mux7:SEL
mux7:OUT
flipflop1:D
flipflop1:CLK
flipflop1:Q
flipflop1:NOTQ
mux2:A
mux2:B
mux2:SEL
mux2:OUT
flipflop7:D
flipflop7:CLK
flipflop7:Q
flipflop7:NOTQ
mux8:A
mux8:B
mux8:SEL
mux8:OUT
flipflop8:D
flipflop8:CLK
flipflop8:Q
flipflop8:NOTQ
mux9:A
mux9:B
mux9:SEL
mux9:OUT
flipflop9:D
flipflop9:CLK
flipflop9:Q
flipflop9:NOTQ
mux10:A
mux10:B
mux10:SEL
mux10:OUT
pwr6:GND
flipflop10:D
flipflop10:CLK
flipflop10:Q
flipflop10:NOTQ
mux11:A
mux11:B
mux11:SEL
mux11:OUT
pwr10:VCC
flipflop11:D
flipflop11:CLK
flipflop11:Q
flipflop11:NOTQ
mux12:A
mux12:B
mux12:SEL
mux12:OUT
pwr11:GND
flipflop12:D
flipflop12:CLK
flipflop12:Q
flipflop12:NOTQ
mux13:A
mux13:B
mux13:SEL
mux13:OUT
pwr12:VCC
flipflop13:D
flipflop13:CLK
flipflop13:Q
flipflop13:NOTQ
mux14:A
mux14:B
mux14:SEL
mux14:OUT
pwr13:VCC
mux15:A
mux15:B
mux15:SEL
mux15:OUT
pwr14:VCC
mux16:A
mux16:B
mux16:SEL
mux16:OUT
pwr15:VCC
mux17:A
mux17:B
mux17:SEL
mux17:OUT
pwr16:VCC
mux18:A
mux18:B
mux18:SEL
mux18:OUT
pwr17:VCC
logic1:D0
logic1:D1
logic1:D2
logic1:D3
logic1:D4
logic1:D5
logic1:D6
logic1:D7
logic1:GND
pwr18:GND
led1:A
led1:C
pwr19:GND
led2:A
led2:C
pwr20:GND
led3:A
led3:C
pwr21:GND
led4:A
led4:C
pwr22:GND
led5:A
led5:C
pwr23:GND
led6:A
led6:C
pwr24:GND
led7:A
led7:C
pwr25:GND
led8:A
led8:C
pwr26:GND
led9:A
led9:C
pwr27:GND
led10:A
led10:C
pwr28:GND
led11:A
led11:C
pwr29:GND
led12:A
led12:C
pwr30:GND
led13:A
led13:C
pwr31:GND
led14:A
led14:C
pwr32:GND
led15:A
led15:C
pwr33:GND
led16:A
led16:C
pwr34:GND
ERC Warnings
flipflop10:CLK: Clock driven by combinatorial logic
flipflop11:CLK: Clock driven by combinatorial logic
flipflop12:CLK: Clock driven by combinatorial logic
flipflop13:CLK: Clock driven by combinatorial logic
flipflop1:CLK: Clock driven by combinatorial logic
flipflop2:CLK: Clock driven by combinatorial logic
flipflop3:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop5:CLK: Clock driven by combinatorial logic
flipflop6:CLK: Clock driven by combinatorial logic
3 additional warning(s) hidden