void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}


verilog-blink.ino

diagram.json

/*
 * Debouncer chip on Wokwi - Proof of Concept. 
 *
 * Author: Tim Mathias
 *
 */

module wokwi
#(
    parameter CLOCK_PERIOD_ns    = 100000,  // nanoseconds.
    parameter DEBOUNCE_PERIOD_ms = 10       // milliseconds.
)
(
    input wire clock,
    input wire in,    // Synchronous and noisy input.

    // Optional outputs.
    output reg out,   // Debounced and filtered output.
    output reg edj,   // Goes high for 1 clock cycle on either edge of output. Note: used "edj" because "edge" is a keyword.
    output reg rise,  // Goes high for 1 clock cycle on the rising edge of output.
    output reg fall   // Goes high for 1 clock cycle on the falling edge of output.
);

    //function integer MinBitWidth([1023:0] value);
    //    begin
    //        for (MinBitWidth = 0; value > 0; MinBitWidth = MinBitWidth + 1)
    //        begin
    //            value = value >> 1;
    //        end
    //    end
    //endfunction

    localparam MAX_COUNT_32BITS = DEBOUNCE_PERIOD_ms * 1_000_000 / CLOCK_PERIOD_ns - 2;  // Default type of 32-bits. Subtract 2 because we will be counting down to -1, i.e. when borrow flag is set.

    //localparam COUNTER_BITS = MinBitWidth(MAX_COUNT_32BITS);  // Calculate actual bit width needed.
    localparam COUNTER_BITS = 16;  // Specify actual bit width needed.
    //typedef logic [COUNTER_BITS - 1 : 0] TCounter;
    //localparam TCounter MAX_COUNT = MAX_COUNT_32BITS;  // Assign to a type of the actual bit width (truncation warning from Quartus).
    localparam [15 : 0] MAX_COUNT = MAX_COUNT_32BITS;  // Assign to a type of the actual bit width (truncation warning from Quartus).
    //localparam TCounter ONE = 1;
    localparam [15 : 0] ONE = 1;

    //typedef logic [COUNTER_BITS : 0] TBorrowCounter;  // Extra bit for borrow flag.
    //TBorrowCounter borrow_counter;
    reg [16 : 0] borrow_counter;
    //logic borrow;
    reg borrow;

    wire w_edj;
    wire w_rise;
    wire w_fall;

    initial
    begin
        out = 0;
    end

    always @(posedge clock)
    begin
        borrow_counter[COUNTER_BITS] <= 0;                  // Clear the borrow flag.
        borrow_counter[COUNTER_BITS - 1 : 0] <= MAX_COUNT;  // Freeze counter by default to reduce switching losses when input and output are equal.
        edj <= 0;
        rise <= 0;
        fall <= 0;
        if (borrow)          // If successfully debounced, notify what happened.
        begin
            out <= in;
            edj <= w_edj;    // Goes high for 1 clock cycle on either edge.
            rise <= w_rise;  // Goes high for 1 clock cycle on the rising edge.
            fall <= w_fall;  // Goes high for 1 clock cycle on the falling edge.
        end
        else if (in != out)  // Hysteresis.
        begin
            borrow_counter <= borrow_counter - ONE;  // Only decrement when input and output differ.
        end
    end

    assign borrow = borrow_counter[COUNTER_BITS];

    // Edge detect.
    assign w_edj = in ^ out;
    assign w_rise = in & ~out;
    assign w_fall = ~in & out;

endmodule


debounce.chip.v

Verilog debounce

debounce.chip.json

/*
 * Synchroniser chip on Wokwi - Proof of Concept. 
 *
 * Author: Tim Mathias
 *
 */

module wokwi
#(
    parameter SYNC_BITS = 3  // Number of bits in the synchronisation buffer (2 minimum).
)
(
    input wire clock,
    input wire in,     // Asynchronous input.
    output wire out    // Synchronous output.
);

    localparam SYNC_MSB = SYNC_BITS - 2;

    reg [SYNC_MSB : 0] sync_buffer;

    always @(posedge clock)
    begin
        {out, sync_buffer} <= {sync_buffer, in};
    end

endmodule

sync.chip.v

{
  "name": "Verilog sync",
  "pins": [
    "clock",
    "in",
    "",
    "out"
  ]
}