void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}


verilog-sync.ino

diagram.json

/*
 * Synchroniser chip on Wokwi - Proof of Concept. 
 *
 * Author: Tim Mathias
 *
 */

module wokwi
#(
    parameter SYNC_BITS = 3  // Number of bits in the synchronisation buffer (2 minimum).
)
(
    input wire clock,
    input wire in,     // Asynchronous input.
    output wire out    // Synchronous output.
);

    localparam SYNC_MSB = SYNC_BITS - 2;

    reg [SYNC_MSB : 0] sync_buffer;

    always @(posedge clock)
    begin
        {out, sync_buffer} <= {sync_buffer, in};
    end

endmodule

sync.chip.v

{
  "name": "Verilog sync",
  "pins": [
    "clock",
    "in",
    "",
    "out"
  ]
}