// Copyright (c) maehw, 2022
// wokwi-lookup-table-generator is licensed under the GNU General Public License v3.0
// Copyright and license notices must be preserved. Contributors provide an express grant of patent rights.
/* Let's start with design specific configuration */
#define DESIGN_NUM_USED_INPUTS (4u)
#define DESIGN_NUM_USED_OUTPUTS (7u)
/* Define whether the verification shall halt on the detection of the
* first error (true) or keep on running to the end (false).
*/
#define VERIFICATION_STOP_ON_ERROR (true)
/* This table shall be generated from the truth table!
* Obviously, also design specific.
*/
uint16_t expected_out_val[2 << (DESIGN_NUM_USED_INPUTS-1)] = {
0b1111110,
0b0110000,
0b1101101,
0b1111001,
0b0110011,
0b1011011,
0b0011111,
0b1110000,
0b1101111,
0b1110011,
0b0000000,
0b0000000,
0b0000000,
0b0000000,
0b0000000,
0b0000000,
};
/* Option to pretty print the input value,
* dependent on your design.
*/
#undef VERIFICATION_PRETTY_PRINT_INPUT_VAL
#undef VERIFICATION_PRETTY_PRINT_EXPECTED_OUT_VAL
#undef VERIFICATION_PRETTY_PRINT_REAL_OUT_VAL
// ------------------------------------------------------------------------------
/* Some parameters to tune verification, but actually
* no real need to touch any code below this line
*/
/* As this is run in simulation, baud rate is not that important */
#define SERIAL_BAUDRATE (230400u)
/* These params can be used to control simulation speed;
* getting a correct reading the 7-segment display on my device takes quite some time.
*/
#define VERIFICATION_SETUP_TIME_MS (50u)
#define VERIFICATION_HOLD_TIME_MS (350u)
// ------------------------------------------------------------------------------
/* No real need to touch any code below this line */
/* The mapping of 10 input and 10 output pins each could be static;
* however, this limits support to designs with <= 10 input and <= 10 output pins,
* instead of limiting the support to designs with an overall pin count of 20!
*/
#define DESIGN_IN_0 ( 2)
#define DESIGN_IN_1 ( 3)
#define DESIGN_IN_2 ( 4)
#define DESIGN_IN_3 ( 5)
#define DESIGN_IN_4 ( 6)
#define DESIGN_IN_5 ( 7)
#define DESIGN_IN_6 ( 8)
#define DESIGN_IN_7 ( 9)
#define DESIGN_IN_8 (10)
#define DESIGN_IN_9 (11)
#define DESIGN_OUT_0 (12)
#define DESIGN_OUT_1 (13)
#define DESIGN_OUT_2 (14)
#define DESIGN_OUT_3 (15)
#define DESIGN_OUT_4 (16)
#define DESIGN_OUT_5 (17)
#define DESIGN_OUT_6 (18)
#define DESIGN_OUT_7 (19)
#define DESIGN_OUT_8 (20)
#define DESIGN_OUT_9 (21)
void setup()
{
const bool stop_verification_on_error = VERIFICATION_STOP_ON_ERROR;
bool tests_passed = true; /* asume the best for the start */
Serial.begin(SERIAL_BAUDRATE);
pinMode(DESIGN_IN_0, OUTPUT);
pinMode(DESIGN_IN_1, OUTPUT);
pinMode(DESIGN_IN_2, OUTPUT);
pinMode(DESIGN_IN_3, OUTPUT);
pinMode(DESIGN_IN_4, OUTPUT);
pinMode(DESIGN_IN_5, OUTPUT);
pinMode(DESIGN_IN_6, OUTPUT);
pinMode(DESIGN_IN_7, OUTPUT);
pinMode(DESIGN_IN_8, OUTPUT);
pinMode(DESIGN_IN_9, OUTPUT);
pinMode(DESIGN_OUT_0, INPUT);
pinMode(DESIGN_OUT_1, INPUT);
pinMode(DESIGN_OUT_2, INPUT);
pinMode(DESIGN_OUT_3, INPUT);
pinMode(DESIGN_OUT_4, INPUT);
pinMode(DESIGN_OUT_5, INPUT);
pinMode(DESIGN_OUT_6, INPUT);
pinMode(DESIGN_OUT_7, INPUT);
pinMode(DESIGN_OUT_8, INPUT);
pinMode(DESIGN_OUT_9, INPUT);
Serial.print("Design has ");
Serial.print(DESIGN_NUM_USED_INPUTS, DEC);
Serial.println(" inputs.");
Serial.print("Design has ");
Serial.print(DESIGN_NUM_USED_OUTPUTS, DEC);
Serial.println(" outputs.");
Serial.print("Testing all 2^");
Serial.print(DESIGN_NUM_USED_INPUTS, DEC);
Serial.println(" input combinations.");
Serial.print("Stop verification on error? ");
Serial.println(stop_verification_on_error ? "Yes" : "No");
for(uint16_t in_val = 0; ( in_val < (2 << (DESIGN_NUM_USED_INPUTS-1)) ) &&
( !stop_verification_on_error ||
(stop_verification_on_error && tests_passed) ); in_val++ )
{
set_design_input_val(in_val);
// wait some time before checking outputs
delay(VERIFICATION_SETUP_TIME_MS);
tests_passed &= verify_design_output_val(in_val);
// wait some time before setting next inputs
delay(VERIFICATION_HOLD_TIME_MS);
}
Serial.println();
if(tests_passed)
{
Serial.println("[PASSED]");
}
else
{
Serial.println("[FAILED]");
}
}
void set_design_input_val(uint16_t val)
{
/* Set logic design inputs at Arduino's output pins;
* output the bits via serial later, so that we don't add large delay between the different pins!
*/
if( (DESIGN_NUM_USED_INPUTS-1) >= 0 )
{
digitalWrite(DESIGN_IN_0, val & (1 << DESIGN_NUM_USED_INPUTS-1));
}
if( (DESIGN_NUM_USED_INPUTS-2) >= 0 )
{
digitalWrite(DESIGN_IN_1, val & (1 << DESIGN_NUM_USED_INPUTS-2));
}
if( (DESIGN_NUM_USED_INPUTS-3) >= 0 )
{
digitalWrite(DESIGN_IN_2, val & (1 << DESIGN_NUM_USED_INPUTS-3));
}
if( (DESIGN_NUM_USED_INPUTS-4) >= 0 )
{
digitalWrite(DESIGN_IN_3, val & (1 << DESIGN_NUM_USED_INPUTS-4));
}
if( (DESIGN_NUM_USED_INPUTS-5) >= 0 )
{
digitalWrite(DESIGN_IN_4, val & (1 << DESIGN_NUM_USED_INPUTS-5));
}
if( (DESIGN_NUM_USED_INPUTS-6) >= 0 )
{
digitalWrite(DESIGN_IN_5, val & (1 << DESIGN_NUM_USED_INPUTS-6));
}
if( (DESIGN_NUM_USED_INPUTS-7) >= 0 )
{
digitalWrite(DESIGN_IN_6, val & (1 << DESIGN_NUM_USED_INPUTS-7));
}
if( (DESIGN_NUM_USED_INPUTS-8) >= 0 )
{
digitalWrite(DESIGN_IN_7, val & (1 << DESIGN_NUM_USED_INPUTS-8));
}
if( (DESIGN_NUM_USED_INPUTS-9) >= 0 )
{
digitalWrite(DESIGN_IN_8, val & (1 << DESIGN_NUM_USED_INPUTS-9));
}
if( (DESIGN_NUM_USED_INPUTS-10) >= 0 )
{
digitalWrite(DESIGN_IN_9, val & (1 << DESIGN_NUM_USED_INPUTS-10));
}
Serial.print("\nWrote input: 0b");
for(int8_t bit_index = DESIGN_NUM_USED_INPUTS-1; bit_index >= 0; bit_index--)
{
Serial.print((val >> bit_index) & 1, BIN);
}
#ifdef VERIFICATION_PRETTY_PRINT_INPUT_VAL
VERIFICATION_PRETTY_PRINT_INPUT_VAL(val);
#endif
Serial.println();
}
bool verify_design_output_val(uint16_t in_val)
{
// read value from logic design outputs at Arduino's input pins
uint16_t val = 0;
if( DESIGN_NUM_USED_OUTPUTS >= 1 )
{
val |= digitalRead(DESIGN_OUT_0);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 2 )
{
val |= digitalRead(DESIGN_OUT_1);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 3 )
{
val |= digitalRead(DESIGN_OUT_2);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 4 )
{
val |= digitalRead(DESIGN_OUT_3);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 5 )
{
val |= digitalRead(DESIGN_OUT_4);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 6 )
{
val |= digitalRead(DESIGN_OUT_5);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 7 )
{
val |= digitalRead(DESIGN_OUT_6);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 8 )
{
val |= digitalRead(DESIGN_OUT_7);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 9 )
{
val |= digitalRead(DESIGN_OUT_8);
val <<= 1;
}
if( DESIGN_NUM_USED_OUTPUTS >= 10 )
{
val |= digitalRead(DESIGN_OUT_9);
val <<= 1;
}
/* the last shift is always one too many */
val >>= 1;
Serial.print(" Expected output: 0b");
for(int8_t bit_index = DESIGN_NUM_USED_OUTPUTS-1; bit_index >= 0; bit_index--)
{
Serial.print((expected_out_val[in_val] >> bit_index) & 1, BIN);
}
#ifdef VERIFICATION_PRETTY_PRINT_EXPECTED_OUT_VAL
VERIFICATION_PRETTY_PRINT_EXPECTED_OUT_VAL(expected_out_val[in_val]);
#endif
Serial.println();
Serial.print(" Read back output: 0b");
for(int8_t bit_index = DESIGN_NUM_USED_OUTPUTS-1; bit_index >= 0; bit_index--)
{
Serial.print((val >> bit_index) & 1, BIN);
}
#ifdef VERIFICATION_PRETTY_PRINT_REAL_OUT_VAL
VERIFICATION_PRETTY_PRINT_REAL_OUT_VAL();
#endif
Serial.println();
if(expected_out_val[in_val] == val)
{
Serial.println(" [PASS]");
return true;
}
else
{
Serial.println(" [FAIL]");
return false;
}
}
void loop()
{
/* no need to loop as everything is only required once and therefore
* already done in setup()
*/
}
input_w:IN
input_w:OUT
input_not_w:IN
input_not_w:OUT
input_x:IN
input_x:OUT
input_not_x:IN
input_not_x:OUT
input_y:IN
input_y:OUT
input_not_y:IN
input_not_y:OUT
input_z:IN
input_z:OUT
input_not_z:IN
input_not_z:OUT
gate_and_0:A
gate_and_0:B
gate_and_0:OUT
gate_and_1:A
gate_and_1:B
gate_and_1:OUT
gate_and_2:A
gate_and_2:B
gate_and_2:OUT
gate_and_3:A
gate_and_3:B
gate_and_3:OUT
gate_and_4:A
gate_and_4:B
gate_and_4:OUT
gate_and_5:A
gate_and_5:B
gate_and_5:OUT
gate_and_6:A
gate_and_6:B
gate_and_6:OUT
gate_and_7:A
gate_and_7:B
gate_and_7:OUT
gate_and_8:A
gate_and_8:B
gate_and_8:OUT
gate_and_9:A
gate_and_9:B
gate_and_9:OUT
gate_and_10:A
gate_and_10:B
gate_and_10:OUT
gate_and_11:A
gate_and_11:B
gate_and_11:OUT
gate_and_12:A
gate_and_12:B
gate_and_12:OUT
gate_and_13:A
gate_and_13:B
gate_and_13:OUT
gate_and_14:A
gate_and_14:B
gate_and_14:OUT
gate_and_15:A
gate_and_15:B
gate_and_15:OUT
gate_and_16:A
gate_and_16:B
gate_and_16:OUT
gate_and_17:A
gate_and_17:B
gate_and_17:OUT
gate_and_18:A
gate_and_18:B
gate_and_18:OUT
gate_and_19:A
gate_and_19:B
gate_and_19:OUT
gate_and_20:A
gate_and_20:B
gate_and_20:OUT
gate_and_21:A
gate_and_21:B
gate_and_21:OUT
gate_and_22:A
gate_and_22:B
gate_and_22:OUT
gate_and_23:A
gate_and_23:B
gate_and_23:OUT
gate_and_24:A
gate_and_24:B
gate_and_24:OUT
gate_and_25:A
gate_and_25:B
gate_and_25:OUT
gate_and_26:A
gate_and_26:B
gate_and_26:OUT
gate_and_27:A
gate_and_27:B
gate_and_27:OUT
gate_and_28:A
gate_and_28:B
gate_and_28:OUT
gate_and_29:A
gate_and_29:B
gate_and_29:OUT
gate_and_30:A
gate_and_30:B
gate_and_30:OUT
gate_and_31:A
gate_and_31:B
gate_and_31:OUT
gate_and_32:A
gate_and_32:B
gate_and_32:OUT
gate_and_33:A
gate_and_33:B
gate_and_33:OUT
gate_and_34:A
gate_and_34:B
gate_and_34:OUT
gate_and_35:A
gate_and_35:B
gate_and_35:OUT
gate_and_36:A
gate_and_36:B
gate_and_36:OUT
gate_and_37:A
gate_and_37:B
gate_and_37:OUT
gate_and_38:A
gate_and_38:B
gate_and_38:OUT
gate_and_39:A
gate_and_39:B
gate_and_39:OUT
gate_and_40:A
gate_and_40:B
gate_and_40:OUT
gate_and_41:A
gate_and_41:B
gate_and_41:OUT
gate_and_42:A
gate_and_42:B
gate_and_42:OUT
gate_and_43:A
gate_and_43:B
gate_and_43:OUT
gate_and_44:A
gate_and_44:B
gate_and_44:OUT
gate_and_45:A
gate_and_45:B
gate_and_45:OUT
gate_and_46:A
gate_and_46:B
gate_and_46:OUT
gate_and_47:A
gate_and_47:B
gate_and_47:OUT
gate_and_48:A
gate_and_48:B
gate_and_48:OUT
gate_and_49:A
gate_and_49:B
gate_and_49:OUT
gate_and_50:A
gate_and_50:B
gate_and_50:OUT
gate_and_51:A
gate_and_51:B
gate_and_51:OUT
gate_and_52:A
gate_and_52:B
gate_and_52:OUT
gate_and_53:A
gate_and_53:B
gate_and_53:OUT
gate_and_54:A
gate_and_54:B
gate_and_54:OUT
gate_and_55:A
gate_and_55:B
gate_and_55:OUT
gate_and_56:A
gate_and_56:B
gate_and_56:OUT
gate_and_57:A
gate_and_57:B
gate_and_57:OUT
gate_and_58:A
gate_and_58:B
gate_and_58:OUT
gate_and_59:A
gate_and_59:B
gate_and_59:OUT
gate_and_60:A
gate_and_60:B
gate_and_60:OUT
gate_and_61:A
gate_and_61:B
gate_and_61:OUT
gate_and_62:A
gate_and_62:B
gate_and_62:OUT
gate_and_63:A
gate_and_63:B
gate_and_63:OUT
gate_and_64:A
gate_and_64:B
gate_and_64:OUT
gate_and_65:A
gate_and_65:B
gate_and_65:OUT
gate_and_66:A
gate_and_66:B
gate_and_66:OUT
gate_and_67:A
gate_and_67:B
gate_and_67:OUT
gate_or_0:A
gate_or_0:B
gate_or_0:OUT
gate_or_1:A
gate_or_1:B
gate_or_1:OUT
gate_or_2:A
gate_or_2:B
gate_or_2:OUT
gate_or_3:A
gate_or_3:B
gate_or_3:OUT
gate_or_4:A
gate_or_4:B
gate_or_4:OUT
gate_or_5:A
gate_or_5:B
gate_or_5:OUT
gate_or_6:A
gate_or_6:B
gate_or_6:OUT
gate_or_7:A
gate_or_7:B
gate_or_7:OUT
gate_or_8:A
gate_or_8:B
gate_or_8:OUT
gate_or_9:A
gate_or_9:B
gate_or_9:OUT
gate_or_10:A
gate_or_10:B
gate_or_10:OUT
gate_or_11:A
gate_or_11:B
gate_or_11:OUT
gate_or_12:A
gate_or_12:B
gate_or_12:OUT
gate_or_13:A
gate_or_13:B
gate_or_13:OUT
gate_or_14:A
gate_or_14:B
gate_or_14:OUT
gate_or_15:A
gate_or_15:B
gate_or_15:OUT
gate_or_16:A
gate_or_16:B
gate_or_16:OUT
gate_or_17:A
gate_or_17:B
gate_or_17:OUT
gate_or_18:A
gate_or_18:B
gate_or_18:OUT
output_A:IN
output_A:OUT
output_B:IN
output_B:OUT
output_C:IN
output_C:OUT
output_D:IN
output_D:OUT
output_E:IN
output_E:OUT
output_F:IN
output_F:OUT
output_G:IN
output_G:OUT
mega:SCL
mega:SDA
mega:AREF
mega:GND.1
mega:13
mega:12
mega:11
mega:10
mega:9
mega:8
mega:7
mega:6
mega:5
mega:4
mega:3
mega:2
mega:1
mega:0
mega:14
mega:15
mega:16
mega:17
mega:18
mega:19
mega:20
mega:21
mega:5V.1
mega:5V.2
mega:22
mega:23
mega:24
mega:25
mega:26
mega:27
mega:28
mega:29
mega:30
mega:31
mega:32
mega:33
mega:34
mega:35
mega:36
mega:37
mega:38
mega:39
mega:40
mega:41
mega:42
mega:43
mega:44
mega:45
mega:46
mega:47
mega:48
mega:49
mega:50
mega:51
mega:52
mega:53
mega:GND.4
mega:GND.5
mega:IOREF
mega:RESET
mega:3.3V
mega:5V
mega:GND.2
mega:GND.3
mega:VIN
mega:A0
mega:A1
mega:A2
mega:A3
mega:A4
mega:A5
mega:A6
mega:A7
mega:A8
mega:A9
mega:A10
mega:A11
mega:A12
mega:A13
mega:A14
mega:A15