// Experimenting with custom chips defined in Verilog

void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}


tiny-tapeout-poc-new-internal-pulls.ino

This is an example of
Text Labels for Wokwi.

diagram.json

Digital Input

input-16-pins.chip.json

Digital Output

output-12-pins.chip.json

// Wokwi Custom Chip - For information and examples see:
// https://link.wokwi.com/custom-chips-alpha
//
// SPDX-License-Identifier: MIT
// Copyright (C) 2022 Uri Shaked / wokwi.com

#include "wokwi-api.h"
#include <stdio.h>
#include <stdlib.h>

#define MAXIO 16

typedef struct {
  pin_t ins[MAXIO];
  pin_t outs[MAXIO];
} chip_state_t;

void update_pins(chip_state_t *chip) {
  for (int i = 0; i < MAXIO; i++) {
    pin_write(chip->outs[i], pin_read(chip->ins[i]));
  }
}

static void chip_pin_change(void *user_data, pin_t pin, uint32_t value) {
  update_pins((chip_state_t*)user_data);
}

void chip_init() {
  chip_state_t *chip = malloc(sizeof(chip_state_t));

  char name[8];
  for(int i1=0;i1<MAXIO;i1++)
  {
      sprintf(name,"EXTIN%d",i1);
      chip->ins[i1] = pin_init(name, INPUT_PULLDOWN);
  }
  for(int i2=0;i2<MAXIO;i2++)
  {
      sprintf(name,"IN%d",i2);
      chip->outs[i2] = pin_init(name, OUTPUT);
  }

  update_pins(chip);

  pin_watch_config_t watch_config = {
    .edge = BOTH,
    .pin_change = chip_pin_change,
    .user_data = chip,
  };
  for (int i = 0; i < MAXIO; i++) {
    pin_watch(chip->ins[i], &watch_config);
  }
  
  // The following message will appear in the browser's DevTools console:
  printf("Hello from input %i pins!\n",MAXIO);
}



input-16-pins.chip.c

// Wokwi Custom Chip - For information and examples see:
// https://link.wokwi.com/custom-chips-alpha
//
// SPDX-License-Identifier: MIT
// Copyright (C) 2022 Uri Shaked / wokwi.com

#include "wokwi-api.h"
#include <stdio.h>
#include <stdlib.h>

#define MAXIO 12

typedef struct {
  pin_t ins[MAXIO];
  pin_t outs[MAXIO];
} chip_state_t;

void update_pins(chip_state_t *chip) {
  for (int i = 0; i < MAXIO; i++) {
    pin_write(chip->outs[i], pin_read(chip->ins[i]));
  }
}

static void chip_pin_change(void *user_data, pin_t pin, uint32_t value) {
  update_pins((chip_state_t*)user_data);
}

void chip_init() {
  chip_state_t *chip = malloc(sizeof(chip_state_t));

  char name[9];
  for(int i1=0;i1<MAXIO;i1++)
  {
    sprintf(name,"OUT%d",i1);
    chip->ins[i1] = pin_init(name, INPUT);   
  }
  for(int i2=0;i2<MAXIO;i2++)
  {
    sprintf(name,"EXTOUT%d",i2);
    chip->outs[i2] = pin_init(name, OUTPUT);
  }

  update_pins(chip);

  pin_watch_config_t watch_config = {
    .edge = BOTH,
    .pin_change = chip_pin_change,
    .user_data = chip,
  };
  for (int i = 0; i < MAXIO; i++) {
    pin_watch(chip->ins[i], &watch_config);
  }
  
  // The following message will appear in the browser's DevTools console:
  printf("Hello from output %i pins!\n",MAXIO);
}



output-12-pins.chip.c

Mux3

mux3.chip.json

`default_nettype none

module wokwi (
    input  S,
    input  N,
    input  O,
    input  P,
    output C
);

assign C = N ? 0 : (S ? P : O);

endmodule


mux3.chip.v

`default_nettype none

module wokwi(
  input I1,
  input I2,
  output OUT
);

  wire net17;
  wire net25;
  wire net26;
  wire net27;
  wire net28;
  wire net29;
  wire net30;

  assign OUT = net17;

  and_cell gate8 (
    .a (net25),
    .b (net26),
    .out (net27)
  );
  or_cell gate9 (
    .a (net25),
    .b (net26),
    .out (net28)
  );
  and_cell gate10 (
    .a (net28),
    .b (net29),
    .out (net30)
  );
  or_cell gate11 (
    .a (net27),
    .b (net30),
    .out (net29)
  );
  buffer_cell gate12 (
    .in (I2),
    .out (net26)
  );
  buffer_cell gate13 (
    .in (I1),
    .out (net25)
  );
  buffer_cell gate14 (
    .in (net29),
    .out (net17)
  );

endmodule

module buffer_cell (
    input in,
    output out
    );
    assign out = in;
endmodule

module and_cell (
    input a,
    input b,
    output out
    );
    assign out = a & b;
endmodule

module or_cell (
    input a,
    input b,
    output out
    );
    assign out = a | b;
endmodule


cgate.chip.v

{
  "name": "C-gate",
  "author": "Shaos",
  "pins": [
    "I1",
    "I2",
    "",
    "OUT"
  ]
}
