// segment pin definitions
#define SegA 12
#define SegB 11
#define SegC 10
#define SegD 9
#define SegE 8
#define SegF 7
#define SegG 6
// common pins of the four digits definitions
#define Dig1 5
#define Dig2 4
#define Dig3 3
#define Dig4 2
volatile int NUMBER = 1;
volatile int current_digit;
void setup() {
// put your setup code here, to run once:
pinMode(SegA, OUTPUT);
pinMode(SegB, OUTPUT);
pinMode(SegC, OUTPUT);
pinMode(SegD, OUTPUT);
pinMode(SegE, OUTPUT);
pinMode(SegF, OUTPUT);
pinMode(SegG, OUTPUT);
pinMode(Dig1, OUTPUT);
pinMode(Dig2, OUTPUT);
pinMode(Dig3, OUTPUT);
pinMode(Dig4, OUTPUT);
current_digit = 1;
cli();
TCCR1A = 0;
TCCR1B = 0;
TCNT1 = 0;
OCR1A = 2048; // compare match register 16MHz/1024/125Hz
TCCR1B |= (1 << WGM12); // CTC mode
TCCR1B |= (1 << CS12) | (1 << CS10); // 1024 prescaler
TIMSK1 |= (1 << OCIE1A); // enable timer compare interrupt
sei();
}
void loop() {
// put your main code here, to run repeatedly:
}
void setDigit(int i) {
for (int j = Dig4; j <= Dig1; j++)
digitalWrite(j, LOW);
digitalWrite(i, HIGH);
}
ISR(TIMER1_COMPA_vect) {
setDigit(6 - current_digit);
switch (current_digit)
{
case 1:
disp(NUMBER / 1000); // prepare to display digit 1 (most left)
break;
case 2:
disp( (NUMBER / 100) % 10); // prepare to display digit 2
break;
case 3:
disp( (NUMBER / 10) % 10); // prepare to display digit 3
break;
case 4:
disp(NUMBER % 10); // prepare to display digit 4 (most right)
}
current_digit++;
if (current_digit % 5 == 0) {
NUMBER++;
current_digit = 1;
}
}
// void dispNumber(int number) {
// int lastDigitIO=2;
// while(number>0&&number<=9999) {
// digitalWrite(lastDigitIO, HIGH);
// disp(number%10);
// number=(number-number%10)/10;
// lastDigitIO++;
// }
// }
void disp(byte number)
{
switch (number)
{
case 0: // print 0
digitalWrite(SegA, LOW);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, LOW);
digitalWrite(SegE, LOW);
digitalWrite(SegF, LOW);
digitalWrite(SegG, HIGH);
break;
case 1: // print 1
digitalWrite(SegA, HIGH);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, HIGH);
digitalWrite(SegE, HIGH);
digitalWrite(SegF, HIGH);
digitalWrite(SegG, HIGH);
break;
case 2: // print 2
digitalWrite(SegA, LOW);
digitalWrite(SegB, LOW);
digitalWrite(SegC, HIGH);
digitalWrite(SegD, LOW);
digitalWrite(SegE, LOW);
digitalWrite(SegF, HIGH);
digitalWrite(SegG, LOW);
break;
case 3: // print 3
digitalWrite(SegA, LOW);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, LOW);
digitalWrite(SegE, HIGH);
digitalWrite(SegF, HIGH);
digitalWrite(SegG, LOW);
break;
case 4: // print 4
digitalWrite(SegA, HIGH);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, HIGH);
digitalWrite(SegE, HIGH);
digitalWrite(SegF, LOW);
digitalWrite(SegG, LOW);
break;
case 5: // print 5
digitalWrite(SegA, LOW);
digitalWrite(SegB, HIGH);
digitalWrite(SegC, LOW);
digitalWrite(SegD, LOW);
digitalWrite(SegE, HIGH);
digitalWrite(SegF, LOW);
digitalWrite(SegG, LOW);
break;
case 6: // print 6
digitalWrite(SegA, LOW);
digitalWrite(SegB, HIGH);
digitalWrite(SegC, LOW);
digitalWrite(SegD, LOW);
digitalWrite(SegE, LOW);
digitalWrite(SegF, LOW);
digitalWrite(SegG, LOW);
break;
case 7: // print 7
digitalWrite(SegA, LOW);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, HIGH);
digitalWrite(SegE, HIGH);
digitalWrite(SegF, HIGH);
digitalWrite(SegG, HIGH);
break;
case 8: // print 8
digitalWrite(SegA, LOW);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, LOW);
digitalWrite(SegE, LOW);
digitalWrite(SegF, LOW);
digitalWrite(SegG, LOW);
break;
case 9: // print 9
digitalWrite(SegA, LOW);
digitalWrite(SegB, LOW);
digitalWrite(SegC, LOW);
digitalWrite(SegD, LOW);
digitalWrite(SegE, HIGH);
digitalWrite(SegF, LOW);
digitalWrite(SegG, LOW);
}
}
uno:A5.2
uno:A4.2
uno:AREF
uno:GND.1
uno:13
uno:12
uno:11
uno:10
uno:9
uno:8
uno:7
uno:6
uno:5
uno:4
uno:3
uno:2
uno:1
uno:0
uno:IOREF
uno:RESET
uno:3.3V
uno:5V
uno:GND.2
uno:GND.3
uno:VIN
uno:A0
uno:A1
uno:A2
uno:A3
uno:A4
uno:A5
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
sevseg1:DIG1
sevseg1:DIG2
sevseg1:DIG3
sevseg1:DIG4
sevseg1:COM
sevseg1:CLN
r1:1
r1:2
r2:1
r2:2
r3:1
r3:2
r5:1
r5:2
r6:1
r6:2
r7:1
r7:2
r8:1
r8:2