void setup() {
// put your setup code here, to run once:
}
void loop() {
// put your main code here, to run repeatedly:
}
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
clock1:CLK
pwr2:GND
pwr1:VCC
chip1:EXTIN0
chip1:EXTIN1
chip1:EXTIN2
chip1:EXTIN3
chip1:EXTIN4
chip1:EXTIN5
chip1:EXTIN6
chip1:EXTIN7
chip1:IN0
chip1:IN1
chip1:IN2
chip1:IN3
chip1:IN4
chip1:IN5
chip1:IN6
chip1:IN7
chip2:OUT0
chip2:OUT1
chip2:OUT2
chip2:OUT3
chip2:OUT4
chip2:OUT5
chip2:OUT6
chip2:OUT7
chip2:EXTOUT0
chip2:EXTOUT1
chip2:EXTOUT2
chip2:EXTOUT3
chip2:EXTOUT4
chip2:EXTOUT5
chip2:EXTOUT6
chip2:EXTOUT7
sw2:1
sw2:2
sw2:3
btn1:1.l
btn1:2.l
btn1:1.r
btn1:2.r
pwr3:VCC
gate1:A
gate1:B
gate1:OUT
gate2:A
gate2:B
gate2:OUT
gate3:A
gate3:B
gate3:OUT
gate5:IN
gate5:OUT
gate6:IN
gate6:OUT
mux1:A
mux1:B
mux1:SEL
mux1:OUT
flipflop1:D
flipflop1:CLK
flipflop1:Q
flipflop1:NOTQ
pwr4:VCC
pwr5:GND
led1:A
led1:C
led2:A
led2:C
led3:A
led3:C
led4:A
led4:C
gate8:IN
gate8:OUT
mux2:A
mux2:B
mux2:SEL
mux2:OUT
mux3:A
mux3:B
mux3:SEL
mux3:OUT
mux4:A
mux4:B
mux4:SEL
mux4:OUT
mux5:A
mux5:B
mux5:SEL
mux5:OUT
mux6:A
mux6:B
mux6:SEL
mux6:OUT
mux7:A
mux7:B
mux7:SEL
mux7:OUT
mux8:A
mux8:B
mux8:SEL
mux8:OUT
mux9:A
mux9:B
mux9:SEL
mux9:OUT
mux10:A
mux10:B
mux10:SEL
mux10:OUT
mux11:A
mux11:B
mux11:SEL
mux11:OUT
mux12:A
mux12:B
mux12:SEL
mux12:OUT
mux13:A
mux13:B
mux13:SEL
mux13:OUT
flipflop2:D
flipflop2:CLK
flipflop2:Q
flipflop2:NOTQ
mux14:A
mux14:B
mux14:SEL
mux14:OUT
gate4:IN
gate4:OUT
gate7:IN
gate7:OUT
gate9:IN
gate9:OUT
flipflop3:D
flipflop3:CLK
flipflop3:Q
flipflop3:NOTQ
mux15:A
mux15:B
mux15:SEL
mux15:OUT
gate10:IN
gate10:OUT
gate11:IN
gate11:OUT
gate12:IN
gate12:OUT
flipflop4:D
flipflop4:CLK
flipflop4:Q
flipflop4:NOTQ
mux16:A
mux16:B
mux16:SEL
mux16:OUT
gate13:IN
gate13:OUT
gate14:IN
gate14:OUT
gate15:IN
gate15:OUT
flipflop5:D
flipflop5:CLK
flipflop5:Q
flipflop5:NOTQ
mux17:A
mux17:B
mux17:SEL
mux17:OUT
gate16:IN
gate16:OUT
gate17:IN
gate17:OUT
gate18:IN
gate18:OUT
gate19:IN
gate19:OUT
gate20:IN
gate20:OUT
gate21:IN
gate21:OUT
gate22:IN
gate22:OUT
gate23:IN
gate23:OUT
gate24:IN
gate24:OUT
flipflop6:D
flipflop6:CLK
flipflop6:Q
flipflop6:NOTQ
mux18:A
mux18:B
mux18:SEL
mux18:OUT
gate25:IN
gate25:OUT
gate26:IN
gate26:OUT
gate27:IN
gate27:OUT
flipflop7:D
flipflop7:CLK
flipflop7:Q
flipflop7:NOTQ
mux19:A
mux19:B
mux19:SEL
mux19:OUT
gate28:IN
gate28:OUT
gate29:IN
gate29:OUT
gate30:IN
gate30:OUT
flipflop8:D
flipflop8:CLK
flipflop8:Q
flipflop8:NOTQ
mux20:A
mux20:B
mux20:SEL
mux20:OUT
gate31:IN
gate31:OUT
gate32:IN
gate32:OUT
gate33:IN
gate33:OUT
flipflop9:D
flipflop9:CLK
flipflop9:Q
flipflop9:NOTQ
mux21:A
mux21:B
mux21:SEL
mux21:OUT
gate34:IN
gate34:OUT
gate35:IN
gate35:OUT
gate36:IN
gate36:OUT
gate37:IN
gate37:OUT
gate38:IN
gate38:OUT
gate39:IN
gate39:OUT
gate40:IN
gate40:OUT
gate41:IN
gate41:OUT
gate42:IN
gate42:OUT
flipflop10:D
flipflop10:CLK
flipflop10:Q
flipflop10:NOTQ
mux22:A
mux22:B
mux22:SEL
mux22:OUT
gate43:IN
gate43:OUT
gate44:IN
gate44:OUT
gate45:IN
gate45:OUT
flipflop11:D
flipflop11:CLK
flipflop11:Q
flipflop11:NOTQ
mux23:A
mux23:B
mux23:SEL
mux23:OUT
gate46:IN
gate46:OUT
gate47:IN
gate47:OUT
gate48:IN
gate48:OUT
flipflop12:D
flipflop12:CLK
flipflop12:Q
flipflop12:NOTQ
mux24:A
mux24:B
mux24:SEL
mux24:OUT
gate49:IN
gate49:OUT
gate50:IN
gate50:OUT
gate51:IN
gate51:OUT
flipflop13:D
flipflop13:CLK
flipflop13:Q
flipflop13:NOTQ
mux25:A
mux25:B
mux25:SEL
mux25:OUT
gate52:IN
gate52:OUT
gate53:IN
gate53:OUT
gate54:IN
gate54:OUT
gate55:IN
gate55:OUT
gate56:IN
gate56:OUT
gate57:IN
gate57:OUT
gate58:IN
gate58:OUT
gate59:IN
gate59:OUT
gate60:IN
gate60:OUT
flipflop14:D
flipflop14:CLK
flipflop14:Q
flipflop14:NOTQ
mux26:A
mux26:B
mux26:SEL
mux26:OUT
gate61:IN
gate61:OUT
gate62:IN
gate62:OUT
gate63:IN
gate63:OUT
flipflop15:D
flipflop15:CLK
flipflop15:Q
flipflop15:NOTQ
mux27:A
mux27:B
mux27:SEL
mux27:OUT
gate64:IN
gate64:OUT
gate65:IN
gate65:OUT
gate66:IN
gate66:OUT
flipflop16:D
flipflop16:CLK
flipflop16:Q
flipflop16:NOTQ
mux28:A
mux28:B
mux28:SEL
mux28:OUT
gate67:IN
gate67:OUT
gate68:IN
gate68:OUT
gate69:IN
gate69:OUT
flipflop17:D
flipflop17:CLK
flipflop17:Q
flipflop17:NOTQ
mux29:A
mux29:B
mux29:SEL
mux29:OUT
gate70:IN
gate70:OUT
gate71:IN
gate71:OUT
gate72:IN
gate72:OUT
gate73:IN
gate73:OUT
gate74:IN
gate74:OUT
gate75:IN
gate75:OUT
gate76:IN
gate76:OUT
gate77:IN
gate77:OUT
gate78:IN
gate78:OUT
gate79:A
gate79:B
gate79:OUT
gate80:A
gate80:B
gate80:OUT
gate81:A
gate81:B
gate81:OUT
gate82:A
gate82:B
gate82:OUT
gate83:IN
gate83:OUT
gate84:IN
gate84:OUT
gate85:IN
gate85:OUT
gate86:IN
gate86:OUT
gate87:A
gate87:B
gate87:OUT
gate88:A
gate88:B
gate88:OUT
gate89:A
gate89:B
gate89:OUT
gate90:A
gate90:B
gate90:OUT
gate91:A
gate91:B
gate91:OUT
gate92:A
gate92:B
gate92:OUT
gate93:A
gate93:B
gate93:OUT
gate94:A
gate94:B
gate94:OUT
ERC Warnings
flipflop2:CLK: Clock driven by combinatorial logic
flipflop3:CLK: Clock driven by combinatorial logic
flipflop4:CLK: Clock driven by combinatorial logic
flipflop5:CLK: Clock driven by combinatorial logic
flipflop6:CLK: Clock driven by combinatorial logic
flipflop7:CLK: Clock driven by combinatorial logic
flipflop8:CLK: Clock driven by combinatorial logic
flipflop9:CLK: Clock driven by combinatorial logic
flipflop10:CLK: Clock driven by combinatorial logic
flipflop11:CLK: Clock driven by combinatorial logic
6 additional warning(s) hidden