/*
 * Verilog chip on Wokwi - Proof of Concept. 
 *
 * The name of the toplevel module must be `wokwi`, 
 * and all the inputs/outputs must be defined in "lcd.chip.json" in the "pins" section.
 * Only 1-bit inputs/outputs are supported, but you can combine several inputs together
 * into a single internal wire.
 */



module wokwi(
  input CLK,
  output RS,
  output reg E,
  output D4,
  output D5,
  output D6,
  output D7
);

reg [5:0] counter = 6'h0;
reg [3:0] state = 4'h0;
reg [4:0] data;
reg [8:0] commands [0:32];

assign {RS, D7, D6, D5, D4} = data;

localparam
// Commands
CMD_4_BIT_MODE = 5'b00011,
CMD_4_BIT_MODE_2 = 5'b00010,
CMD_DISPLAY_ON = 5'b00000,
CMD_DISPLAY_ON_2 = 5'b01110,
CMD_UPPERCASE = 5'b10100,
CMD_LOWERCASE = 5'b10110,
CMD_DUMMY = 5'b10000,

// Characters
CHAR_A = 5'b10001, CHAR_B = 5'b10010, CHAR_C = 5'b10011, CHAR_D = 5'b10100,
CHAR_E = 5'b10101, CHAR_F = 5'b10110, CHAR_G = 5'b10111, CHAR_H = 5'b11000,
CHAR_I = 5'b11001, CHAR_J = 5'b11010, CHAR_K = 5'b11011, CHAR_L = 5'b11100,
CHAR_M = 5'b11101, CHAR_N = 5'b11110, CHAR_O = 5'b11111, CHAR_P = 5'b10001,
CHAR_Q = 5'b10010, CHAR_R = 5'b10011, CHAR_S = 5'b10100, CHAR_T = 5'b10101,
CHAR_U = 5'b10110, CHAR_V = 5'b10111, CHAR_W = 5'b11000, CHAR_X = 5'b11001,
CHAR_Y = 5'b11010, CHAR_Z = 5'b11011;

initial
begin
    // Initialize the commands array
    commands[0] = CMD_4_BIT_MODE;
    commands[1] = CMD_4_BIT_MODE_2;
    commands[2] = CMD_DISPLAY_ON;
    commands[3] = CMD_DISPLAY_ON_2;

    commands[4] = CMD_UPPERCASE; // Write 'H'
    commands[5] = CHAR_H;

    commands[6] = CMD_LOWERCASE; // Write 'e'
    commands[7] = CHAR_E;

    commands[8] = CMD_LOWERCASE; // Write 'l'
    commands[9] = CHAR_L;

    commands[10] = CMD_LOWERCASE; // Write 'l'
    commands[11] = CHAR_L;

    commands[12] = CMD_LOWERCASE; // Write 'o'
    commands[13] = CHAR_O;

    commands[14] = CMD_DUMMY; // Some dummy data
end

always @(posedge CLK) // Execute on positive edge of clock
begin
    counter <= counter + 1'b1; // Increment counter
    // Wait for counter to reset to 0
    if (counter == 6'b0)
    begin
        E <= 1'b1; // Set enable signal high

        // If not all commands have been sent yet
        if (state < 4'hF)
        begin
            data <= commands[state]; // Load data from commands array
            state <= state + 1'b1; // Increment state
        end else
        begin
            E <= 1'b0; // Set enable signal low
        end
    end else
    begin
        E <= 1'b0; // Set enable signal low
    end
end

endmodule