# Tiny Tapeout 4 SAR ADC

This is a digital backend of a charge redistrbution successive approximation analog to digital converter (SAR ADC).
A SAR ADC converts an analog voltage to a digital value by successively recreating better and better
approximations of the input analog signal. This is done by connecting capacitors of decreasing
value to a big capacitor with the original analog value stored. It will create a capacitive 
divider and a new voltage. This voltage is sent to a comparator and compared with a 
reference voltage. The comparators output goes in to the digital backend through IN0. 
See Wikipedia for better explanation: https://en.wikipedia.org/wiki/Successive-approximation_ADC 


There are two ways to interface with the ADC:

1. With a 6 or 11 bit paralell bus
To make a measurement, D0 (aka "Start"), needs to be pulsed High. 
While the measurement is taking place the pin will remain high as to signal that it is busy.
When the pin goes low, the measurement is done. 
Read the measurement by storing OUT0 through OUT7 and D3 through D7. OUT0 is MSB and D7 is LSB. 

The precision of the ADC can be set to either 11 bits or 6 bits for faster measurements. 
When IN1 is low, the ADC is in 11 bit mode. When IN2 is high, the ADC is in 6 bit mode.

2. Through I2C
Connect D1 to SCL of a MCU and D2 to SDA. Make sure to have pullups. 
The I2C address of the ADC can be configured to either 0x34 or 0x35. 
When IN2 is high, the address is 0x34 and when it is low it is 0x35.
To make a measurement, send a write command to configured address with the data 0x01.
Read the measurement by requesting 2 bytes from configured address. 
It will NACK the request if it is still busy with the measurement. 


More documentation to come...
5
D0
D3
D4
D5
D6
D7
Busy
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
MSB
LSB
LSB
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
MSB
SR
SR
D1
D2
MSB
LSB or R/W
R
W
Ack out
Listening
Idle
SR
SR
SR
SR
NACK reset
Reading addr
SR
SR
SDA
SCL
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
Pause for ACK
LSB
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
SR
MSB
SR
SR
Ready
SR
SR
SR

ERC Warnings

flop2:CLK: Clock driven by combinatorial logic
flop1:CLK: Clock driven by combinatorial logic
flop6:CLK: Clock driven by combinatorial logic
flop5:CLK: Clock driven by combinatorial logic
flop4:CLK: Clock driven by combinatorial logic
flop3:CLK: Clock driven by combinatorial logic
flop13:CLK: Clock driven by combinatorial logic
flop14:CLK: Clock driven by combinatorial logic
flop17:CLK: Clock driven by combinatorial logic
flop18:CLK: Clock driven by combinatorial logic
50 additional warning(s) hidden