# Blank project
This is a blank Wokwi project. Please edit this README file and add a description of your project.
## Usage
1. Add parts by clicking the blue "+" button in the diagram editor
2. Connect parts by dragging wires between them
3. Click the green play button to start the simulation
sw1:1a
sw1:2a
sw1:3a
sw1:4a
sw1:5a
sw1:6a
sw1:7a
sw1:8a
sw1:8b
sw1:7b
sw1:6b
sw1:5b
sw1:4b
sw1:3b
sw1:2b
sw1:1b
vcc1:VCC
r1:1
r1:2
r2:1
r2:2
r3:1
r3:2
r4:1
r4:2
r5:1
r5:2
r6:1
r6:2
r7:1
r7:2
r8:1
r8:2
gnd1:GND
not1:IN
not1:OUT
sw2:1a
sw2:2a
sw2:3a
sw2:4a
sw2:5a
sw2:6a
sw2:7a
sw2:8a
sw2:8b
sw2:7b
sw2:6b
sw2:5b
sw2:4b
sw2:3b
sw2:2b
sw2:1b
r9:1
r9:2
r10:1
r10:2
r11:1
r11:2
r12:1
r12:2
r13:1
r13:2
r14:1
r14:2
r15:1
r15:2
r16:1
r16:2
or1:A
or1:B
or1:OUT
flop1:D
flop1:CLK
flop1:Q
flop1:NOTQ
flop2:D
flop2:CLK
flop2:S
flop2:R
flop2:Q
flop2:NOTQ
flop3:D
flop3:CLK
flop3:S
flop3:R
flop3:Q
flop3:NOTQ
mux1:A
mux1:B
mux1:SEL
mux1:OUT
mux2:A
mux2:B
mux2:SEL
mux2:OUT
mux3:A
mux3:B
mux3:SEL
mux3:OUT
mux4:A
mux4:B
mux4:SEL
mux4:OUT
mux5:A
mux5:B
mux5:SEL
mux5:OUT
mux6:A
mux6:B
mux6:SEL
mux6:OUT
mux7:A
mux7:B
mux7:SEL
mux7:OUT
mux8:A
mux8:B
mux8:SEL
mux8:OUT
mux9:A
mux9:B
mux9:SEL
mux9:OUT
mux10:A
mux10:B
mux10:SEL
mux10:OUT
mux11:A
mux11:B
mux11:SEL
mux11:OUT
mux12:A
mux12:B
mux12:SEL
mux12:OUT
mux13:A
mux13:B
mux13:SEL
mux13:OUT
mux14:A
mux14:B
mux14:SEL
mux14:OUT
mux15:A
mux15:B
mux15:SEL
mux15:OUT
mux16:A
mux16:B
mux16:SEL
mux16:OUT
flop4:D
flop4:CLK
flop4:S
flop4:R
flop4:Q
flop4:NOTQ
and1:A
and1:B
and1:OUT
flop5:D
flop5:CLK
flop5:Q
flop5:NOTQ
gnd2:GND
mux17:A
mux17:B
mux17:SEL
mux17:OUT
mux18:A
mux18:B
mux18:SEL
mux18:OUT
flop6:D
flop6:CLK
flop6:S
flop6:R
flop6:Q
flop6:NOTQ
flop7:D
flop7:CLK
flop7:S
flop7:R
flop7:Q
flop7:NOTQ
mux19:A
mux19:B
mux19:SEL
mux19:OUT
mux20:A
mux20:B
mux20:SEL
mux20:OUT
flop8:D
flop8:CLK
flop8:S
flop8:R
flop8:Q
flop8:NOTQ
flop9:D
flop9:CLK
flop9:S
flop9:R
flop9:Q
flop9:NOTQ
mux21:A
mux21:B
mux21:SEL
mux21:OUT
mux22:A
mux22:B
mux22:SEL
mux22:OUT
flop10:D
flop10:CLK
flop10:S
flop10:R
flop10:Q
flop10:NOTQ
flop11:D
flop11:CLK
flop11:S
flop11:R
flop11:Q
flop11:NOTQ
mux23:A
mux23:B
mux23:SEL
mux23:OUT
mux24:A
mux24:B
mux24:SEL
mux24:OUT
flop12:D
flop12:CLK
flop12:S
flop12:R
flop12:Q
flop12:NOTQ
flop13:D
flop13:CLK
flop13:S
flop13:R
flop13:Q
flop13:NOTQ
mux25:A
mux25:B
mux25:SEL
mux25:OUT
mux26:A
mux26:B
mux26:SEL
mux26:OUT
flop14:D
flop14:CLK
flop14:S
flop14:R
flop14:Q
flop14:NOTQ
flop15:D
flop15:CLK
flop15:S
flop15:R
flop15:Q
flop15:NOTQ
mux27:A
mux27:B
mux27:SEL
mux27:OUT
mux28:A
mux28:B
mux28:SEL
mux28:OUT
flop16:D
flop16:CLK
flop16:S
flop16:R
flop16:Q
flop16:NOTQ
flop17:D
flop17:CLK
flop17:S
flop17:R
flop17:Q
flop17:NOTQ
mux29:A
mux29:B
mux29:SEL
mux29:OUT
mux30:A
mux30:B
mux30:SEL
mux30:OUT
flop18:D
flop18:CLK
flop18:S
flop18:R
flop18:Q
flop18:NOTQ
flop19:D
flop19:CLK
flop19:S
flop19:R
flop19:Q
flop19:NOTQ
mux31:A
mux31:B
mux31:SEL
mux31:OUT
mux32:A
mux32:B
mux32:SEL
mux32:OUT
and2:A
and2:B
and2:OUT
and3:A
and3:B
and3:OUT
and4:A
and4:B
and4:OUT
and5:A
and5:B
and5:OUT
and6:A
and6:B
and6:OUT
and7:A
and7:B
and7:OUT
and8:A
and8:B
and8:OUT
and9:A
and9:B
and9:OUT
and10:A
and10:B
and10:OUT
and11:A
and11:B
and11:OUT
and12:A
and12:B
and12:OUT
and13:A
and13:B
and13:OUT
and14:A
and14:B
and14:OUT
and15:A
and15:B
and15:OUT
and16:A
and16:B
and16:OUT
clock1:CLK
btn2:1.l
btn2:2.l
btn2:1.r
btn2:2.r
gnd3:GND
r17:1
r17:2
pwr3:VCC
led1:A
led1:C
gnd4:GND
ERC Warnings
flop2:S: Input pin not driven
flop3:S: Input pin not driven
flop4:S: Input pin not driven
flop4:R: Input pin not driven
flop6:S: Input pin not driven
flop7:S: Input pin not driven
flop8:S: Input pin not driven
flop9:S: Input pin not driven
flop10:S: Input pin not driven
flop11:S: Input pin not driven
11 additional warning(s) hidden