{
  "version": 1,
  "author": "Anonymous maker",
  "editor": "wokwi",
  "parts": [
    { "type": "wokwi-gate-and-2", "id": "and1", "top": 48, "left": 249.6, "attrs": {} },
    {
      "type": "board-tt-block-input",
      "id": "chip1",
      "top": 2.27,
      "left": -100.8,
      "attrs": { "verilogRole": "input" }
    },
    {
      "type": "board-tt-block-output",
      "id": "chip2",
      "top": 21.47,
      "left": 388.8,
      "attrs": { "verilogRole": "output" }
    },
    { "type": "wokwi-gate-or-2", "id": "or1", "top": 96, "left": 105.6, "attrs": {} },
    { "type": "wokwi-gate-or-2", "id": "or2", "top": 9.6, "left": 105.6, "attrs": {} }
  ],
  "connections": [
    [ "or2:OUT", "and1:A", "green", [ "v0", "h48" ] ],
    [ "or1:OUT", "and1:B", "green", [ "v0", "h48" ] ],
    [ "chip1:IN0", "or2:A", "green", [ "h48", "v-28.8", "h0" ] ],
    [ "chip1:IN1", "or2:B", "green", [ "h105.6" ] ],
    [ "chip1:IN2", "or1:A", "green", [ "h67.2", "v0", "h38.4" ] ],
    [ "and1:OUT", "chip2:OUT0", "green", [ "v-19.2", "h48" ] ],
    [ "chip1:IN3", "or1:B", "green", [ "h57.6", "v48" ] ]
  ],
  "dependencies": {}
}