# Lab 2 (Part 2) - Exercise 10

## Question

1. Realize NOT, AND & OR gates only using 2 input NAND gate(s)?

## Solution

### Truth Table of 1 input NOT gate - `Y = A'`

| A | Y |
|---|---|
| 0 | 1 |
| 1 | 0 |

### Truth Table of 2 input AND gate - `Y = A.B`

| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |

### Truth Table of 2 input OR gate - `Y = A+B`

| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |