# Lab 2 (Part 2) - Exercise 11

## Question

1. Realize NOT, OR & AND gates only using 2 input NOR gate(s)?

## Solution

* Here NOR gate is implemented using OR & NOT.

### Truth Table of 1 input NOT gate - `Y = A'`

| A | Y |
|---|---|
| 0 | 1 |
| 1 | 0 |

### Truth Table of 2 input OR gate - `Y = A+B`

| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |

### Truth Table of 2 input AND gate - `Y = A.B`

| A | B | Y |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
led1:A
led1:C
gnd1:GND
vcc1:VCC
sw1:1
sw1:2
sw1:3
or1:A
or1:B
or1:OUT
vcc2:VCC
led2:A
led2:C
gnd2:GND
or2:A
or2:B
or2:OUT
or3:A
or3:B
or3:OUT
sw2:1
sw2:2
sw2:3
sw3:1
sw3:2
sw3:3
vcc3:VCC
led3:A
led3:C
gnd3:GND
or4:A
or4:B
or4:OUT
or5:A
or5:B
or5:OUT
or6:A
or6:B
or6:OUT
sw4:1
sw4:2
sw4:3
sw5:1
sw5:2
sw5:3
not1:IN
not1:OUT
not2:IN
not2:OUT
not3:IN
not3:OUT
not4:IN
not4:OUT
not5:IN
not5:OUT
not6:IN
not6:OUT