# Lab 4 - Exercise 2

## Question

1. We need to create chip design of the Hot Coffee/Hot Milk Dispenser machine using it's boolean expressions given below:
* Final Expressions after solving K-Maps implemented here using logic gates are:
  * `Coff_Out(CREQ, MREQ, M, T, C) = CREQ.M.T'.C` 
  * `Milk_Out(CREQ, MREQ, M, T, C) = MREQ.M.T'`
  * `Insuff_Qty(CREQ, MREQ, M, T, C) = MREQ.M' + CREQ.(M' + C')`

## Solution

Code to add to parts section of `diagram.json` for adding chip IN and chip OUT:
```json
{ "type": "board-tt-block-input", "id": "chip1", "top": 242.27, "left": 292.8, "attrs": { "verilogRole": "input" }},
{ "type": "board-tt-block-output", "id": "chip2", "top": 290.27, "left": 792, "attrs": { "verilogRole": "output" }},
```

Link to verilog code: [https://wokwi.com/api/projects/385541309817051137/verilog](https://wokwi.com/api/projects/385541309817051137/verilog)

```verilog
/* Automatically generated from https://wokwi.com/projects/385541309817051137 */

`default_nettype none

module tt_um_wokwi_385541309817051137(
  input  wire [7:0] ui_in,    // Dedicated inputs
  output wire [7:0] uo_out,    // Dedicated outputs
  input  wire [7:0] uio_in,    // IOs: Input path
  output wire [7:0] uio_out,    // IOs: Output path
  output wire [7:0] uio_oe,    // IOs: Enable path (active high: 0=input, 1=output)
  input ena,
  input clk,
  input rst_n
);
  wire net1 = ui_in[0];
  wire net2 = ui_in[1];
  wire net3 = ui_in[2];
  wire net4 = ui_in[3];
  wire net5 = ui_in[4];
  wire net6;
  wire net7;
  wire net8;
  wire net9;
  wire net10;
  wire net11;
  wire net12;
  wire net13;
  wire net14;
  wire net15;
  wire net16;
  wire net17;

  assign uo_out[0] = net6;
  assign uo_out[1] = net7;
  assign uo_out[2] = net8;
  assign uo_out[3] = 0;
  assign uo_out[4] = 0;
  assign uo_out[5] = 0;
  assign uo_out[6] = 0;
  assign uo_out[7] = 0;
  assign uio_out[0] = 0;
  assign uio_oe[0] = 0;
  assign uio_out[1] = 0;
  assign uio_oe[1] = 0;
  assign uio_out[2] = 0;
  assign uio_oe[2] = 0;
  assign uio_out[3] = 0;
  assign uio_oe[3] = 0;
  assign uio_out[4] = 0;
  assign uio_oe[4] = 0;
  assign uio_out[5] = 0;
  assign uio_oe[5] = 0;
  assign uio_out[6] = 0;
  assign uio_oe[6] = 0;
  assign uio_out[7] = 0;
  assign uio_oe[7] = 0;

  not_cell not2 (
    .in (net3),
    .out (net9)
  );
  not_cell not3 (
    .in (net4),
    .out (net10)
  );
  not_cell not4 (
    .in (net5),
    .out (net11)
  );
  and_cell and1 (
    .a (net1),
    .b (net3),
    .out (net12)
  );
  and_cell and2 (
    .a (net12),
    .b (net10),
    .out (net13)
  );
  and_cell and3 (
    .a (net13),
    .b (net5),
    .out (net6)
  );
  and_cell and4 (
    .a (net2),
    .b (net3),
    .out (net14)
  );
  and_cell and5 (
    .a (net14),
    .b (net10),
    .out (net7)
  );
  or_cell or1 (
    .a (net9),
    .b (net11),
    .out (net15)
  );
  and_cell and6 (
    .a (net1),
    .b (net15),
    .out (net16)
  );
  or_cell or2 (
    .a (net17),
    .b (net16),
    .out (net8)
  );
  and_cell and7 (
    .a (net2),
    .b (net9),
    .out (net17)
  );
endmodule
```