from machine import Pin
from time import sleep
# Define GPIO pin numbers for rows and columns
cols = [0, 2, 4] # Adjust as needed
rows = [6, 8, 10, 12, 14, 15] # Adjust as needed
# Set up rows as outputs and columns as inputs with pull-up resistors
for row_pin in rows:
Pin(row_pin, Pin.OUT)
for col_pin in cols:
Pin(col_pin, mode=Pin.IN, pull=Pin.PULL_UP)
# Define the layout mapping
layout_mapping = {
(6, 0): 1,
(6, 2): 2,
(6, 4): 3,
(8, 0): 4,
(8, 2): 5,
(8, 4): 6,
(10, 0): 7,
(10, 2): 8,
(10, 4): 9,
(12, 2): 0,
(14, 0): "x",
(14, 4): "✓",
(15, 2): "◄"
}
segments = {
"CT": 28,
"TR": 27,
"BR": 26,
"CB": 22,
"BL": 21,
"TL": 20,
"CM": 19,
"DP": 18,
}
states = {
"1": [0, 1, 1, 0, 0, 0, 0],
"2": [1, 1, 0, 1, 1, 0, 1],
"3": [1, 1, 1, 1, 0, 0, 1],
"4": [0, 1, 1, 0, 0, 1, 1],
"5": [1, 0, 1, 1, 0, 1, 1],
"6": [1, 0, 1, 1, 1, 1, 1],
"7": [1, 1, 1, 0, 0, 0, 0],
"8": [1, 1, 1, 1, 1, 1, 1],
"9": [1, 1, 1, 1, 0, 1, 1],
"0": [1, 1, 1, 1, 1, 1, 0]
}
while True:
for row_pin in rows:
# Set the current row to LOW
Pin(row_pin, Pin.OUT).value(0)
# Check the state of each column
for col_pin in cols:
button_state = Pin(col_pin).value()
if button_state == 0:
button_number = layout_mapping.get((row_pin, col_pin), None)
print(button_number)
segment_decision = [(state, segments[segment]) for state, segment in zip(states[str(button_number)], ["CT", "TR", "BR", "CB", "BL", "TL", "CM", "DP"])]
if button_number is not None and button_number not in ["x", "✓", "◄"]:
for i in segment_decision:
num = Pin(i[1], Pin.OUT)
num.value(i[0])
# Set the current row back to HIGH
Pin(row_pin, Pin.OUT).value(1)
sleep(0.01) # Adjust the delay as needed
pico:GP0
pico:GP1
pico:GND.1
pico:GP2
pico:GP3
pico:GP4
pico:GP5
pico:GND.2
pico:GP6
pico:GP7
pico:GP8
pico:GP9
pico:GND.3
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pico:GP11
pico:GP12
pico:GP13
pico:GND.4
pico:GP14
pico:GP15
pico:GP16
pico:GP17
pico:GND.5
pico:GP18
pico:GP19
pico:GP20
pico:GP21
pico:GND.6
pico:GP22
pico:RUN
pico:GP26
pico:GP27
pico:GND.7
pico:GP28
pico:ADC_VREF
pico:3V3
pico:3V3_EN
pico:GND.8
pico:VSYS
pico:VBUS
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btn13:1.l
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sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP