// RM0008 #include "m3.h" #include // rcc register map (page 12) typedef struct {volatile uint32_t CR, CFGR, CIR, APB2RSTR, APB1RSTR, AHBENR, APB2ENR, // APB1ENR, BDCR, CSR; } rcc_t; // section 7.3.1 typedef enum { HSION = 0, HSIRDY, HSITRIM_0 = 3, HSITRIM_1, HSITRIM_2, HSITRIM_3, HSITRIM_4, HSICAL_0, HSICAL_1, HSICAL_2, HSICAL_3, HSICAL_4, HSICAL_5, HSICAL_6, HSICAL_7, HSEON, HSERDY, HSEBYP, CSSON, PLLON = 24, PLLRDY } rcc_cr_t; // section 7.3.2 typedef enum { SW_0, SW_1, SWS_0, SWS_1, HPRE_0, HPRE_1, HPRE_2, HPRE_3, PPRE1_0, PPRE1_1, PPRE1_2, PPRE2_0, PPRE2_1, PPRE2_2, ADCPRE_0, ADCPRE_1, PLLSRC, PLLXTPRE, PLLMUL_0, PLLMUL_1, PLLMUL_2, USBPRE, MCO_0, MCO_1, MCO_2, PLLRDY, } CFGR_t; #define SW_HSI 0 #define SW_HSE 1 #define SW_PLL 2 #define HPRE_DIV1 0 #define HPRE_DIV2 (8 << HPRE_0) #define HPRE_DIV4 (9 << HPRE_0) #define HPRE_DIV8 (10 << HPRE_0) #define HPRE_DIV16 (11 << HPRE_0) #define HPRE_DIV64 (12 << HPRE_0) #define HPRE_DIV128 (13 << HPRE_0) #define HPRE_DIV256 (14 << HPRE_0) #define HPRE_DIV512 (15 << HPRE_0) #define PPRE1_DIV1 0 #define PPRE1_DIV2 (4 << PPRE1_0) #define PPRE1_DIV4 (5 << PPRE1_0) #define PPRE1_DIV8 (6 << PPRE1_0) #define PPRE1_DIV16 (7 << PPRE1_0) #define PPRE2_DIV1 0 #define PPRE2_DIV2 (4 << PPRE1_0) #define PPRE2_DIV4 (5 << PPRE1_0) #define PPRE2_DIV8 (6 << PPRE1_0) #define PPRE2_DIV16 (7 << PPRE1_0) #define ADCPRE_DIV2 0 #define ADCPRE_DIV4 (1 << ADCPRE_0) #define ADCPRE_DIV6 (2 << ADCPRE_0) #define ADCPRE_DIV8 (3 << ADCPRE_0) #define PLL_MULL2 (0 << PLLMUL_0) #define PLL_MULL3 (1 << PLLMUL_0) #define PLL_MULL4 (2 << PLLMUL_0) #define PLL_MULL5 (3 << PLLMUL_0) #define PLL_MULL6 (4 << PLLMUL_0) #define PLL_MULL7 (5 << PLLMUL_0) #define PLL_MULL8 (6 << PLLMUL_0) #define PLL_MULL9 (7 << PLLMUL_0) #define PLL_MULL10 (8 << PLLMUL_0) #define PLL_MULL11 (9 << PLLMUL_0) #define PLL_MULL12 (10 << PLLMUL_0) #define PLL_MULL13 (11 << PLLMUL_0) #define PLL_MULL14 (12 << PLLMUL_0) #define PLL_MULL15 (13 << PLLMUL_0) #define PLL_MULL16 (14 << PLLMUL_0) typedef enum { AFIOEN = 0, IOPAEN = 2, IOPBEN, IOPCEN, IOPDEN, IOPEEN, IOPFEN, IOPGEN, ADC1EN, ADC2EN, TIM1EN, SPI1EN, TIM8EN, USART1EN, ADC3EN, TIM9EN = 19, TIM10EN, TIM11EN } APB2ENR_t; // section 9.5 gpio and afio register map typedef struct {volatile uint32_t CRL, CRH, IDR, ODR, BSRR, BRR, LCKR; } gpio_t; typedef enum { INPUT, OUTPUT_10MHZ, OUTPUT_2MHZ, OUTPUT_50MHZ, } gpio_crx_mod_t; typedef enum { INPUT_ANALOG = 0, INPUT_FLOAT = 1, INPUT_PULL = 2, OUTPUT_PUSHPULL = 0, OUTPUT_OPENDRAIN = 1, ALTERNATE_OUTPUT_PUSHPULL = 2, ALTERNATE_OUTPUT_OPENDRAIN = 3, } gpio_crx_cnf_t; // flash memory (page 54) typedef struct {volatile uint32_t ACR, KEYR, OPTKEYR, SR, CR, AR, _r0, OBR, WRPR; } flash_t; typedef enum { LATENCY_0, LATENCY_1, LATENCY_2, HLFCYA, PRFTBE, PRFTBS } flash_acr_t; typedef enum { LATENCY_NO_WAIT_STATES = 0 << LATENCY_0, LATENCY_1_WAIT_STATE = 2 << LATENCY_0, LATENCY_2_WAIT_STATES = 4 << LATENCY_0, } flash_acr_latency_t; // memory map (page 50) #define RCC ((rcc_t *) 0x40021000) #define GPIO(x) ((gpio_t *) (0x40010800 + 0x400 * (x))) #define FLASH ((flash_t *) 0x40022000) #include "narduino.h" // GPIO void port_enable(port_t port) { if (port == PortA) RCC->APB2ENR |= bit(IOPAEN); if (port == PortB) RCC->APB2ENR |= bit(IOPBEN); if (port == PortC) RCC->APB2ENR |= bit(IOPCEN); if (port == PortD) RCC->APB2ENR |= bit(IOPDEN); } void pin_mode(pin_t pin, pin_mode_t mode) { gpio_crx_mod_t mod; gpio_crx_cnf_t cnf; switch (mode) { case Input: mod = INPUT; cnf = INPUT_FLOAT; break; case InputPullUp: mod = INPUT; cnf = INPUT_PULL; break; case InputPullDown: mod = INPUT; cnf = INPUT_PULL; break; case InputAnalog: mod = INPUT; cnf = INPUT_ANALOG; break; case Output: mod = OUTPUT_10MHZ; cnf = OUTPUT_PUSHPULL; break; case OutputOpenDrain: mod = OUTPUT_10MHZ; cnf = OUTPUT_OPENDRAIN; break; case AlternateOutput: mode = OUTPUT_10MHZ; cnf = ALTERNATE_OUTPUT_PUSHPULL; break; case AlternateOutputOpenDrain: mod = OUTPUT_10MHZ; cnf = ALTERNATE_OUTPUT_OPENDRAIN; break; } uint32_t val, mask; gpio_t * gpio = GPIO(port_nr(pin)); if (pin < 8) { val = ((cnf << 2) + mod) << (4 * pin_nr(pin)); mask = 0xf << (4 * pin_nr(pin)); gpio->CRL = (gpio->CRL & ~mask) | val; } else { val = ((cnf << 2) + mod) << (4 * (pin_nr(pin) - 8)); mask = 0xf << (4 * (pin_nr(pin) - 8)); gpio->CRH = (gpio->CRH & ~mask) | val; } } void pin_set(pin_t pin) { gpio_t * gpio = GPIO(port_nr(pin)); gpio->BSRR |= pin_mask(pin); } void pin_reset(pin_t pin) { gpio_t * gpio = GPIO(port_nr(pin)); gpio->BRR |= pin_mask(pin); } void system_init() { //FLASH->ACR &=~FLASH_ACR_LATENCY_0; // latency 2 wait states //FLASH->ACR |= FLASH_ACR_LATENCY_1; FLASH->ACR |= LATENCY_2_WAIT_STATES; RCC->CR |= bit(HSEON); // enable hse while (!(RCC->CR & bit(HSERDY))); RCC->CFGR |= bit(PLLSRC) // HSE as PLL input | PPRE1_DIV2 // APB1 prescale 2 (<36MHz) | PLL_MULL9; // clk = 8 * 9 = 72Mhz RCC->CR |= bit(PLLON); while (!(RCC->CR & bit(PLLRDY))); RCC->CFGR |= SW_PLL; // PLL as system clock source systick_init(71999); } rcc.apb2enr.iopaen = 1; rcc.cfgr.pllsrc =