readme.md

diagram.json

#include "gpio.h"
#include "stm32l0x1.h"
#include <stdint.h>

typedef enum {
	INPUT, OUTPUT, ALTERNATE, ANALOG
} gpio_mode_t;

typedef enum {
	PUSH_PULL, OPEN_DRAIN,
} gpio_otype_t;

typedef enum {
	LOW_SPEED,	MEDIUM_SPEED, HIGH_SPEED, VERY_HIGH_SPEED,
} gpio_ospeed_t;

typedef enum {
	NO_PULL, PULL_UP, PULL_DOWN,
} gpio_pull_t;

static inline void gpio_mode(pin_t pin, gpio_mode_t mode) {
	gpio_t * gpio = GPIO(pin_port(pin));
	gpio->MODER = (gpio->MODER & ~pin_mask2(pin)) | (mode << (2 * pin_number(pin)));
}

static inline void gpio_otype(pin_t pin, gpio_otype_t otype) {
	gpio_t * gpio = GPIO(pin_port(pin));
	gpio->OTYPER = (gpio->OTYPER & ~pin_mask(pin)) | (otype << pin_number(pin));
}

static inline void gpio_ospeed(pin_t pin, gpio_ospeed_t ospeed) {
	gpio_t * gpio = GPIO(pin_port(pin));
	gpio->OSPEEDR = (gpio->OSPEEDR & ~pin_mask2(pin)) | (ospeed << (2 * pin_number(pin)));
}

static inline void gpio_pull(pin_t pin, gpio_pull_t pull) {
	gpio_t * gpio = GPIO(pin_port(pin));	
	gpio->PUPDR = (gpio->PUPDR & ~pin_mask2(pin)) | (pull << (2 * pin_number(pin)));
}

void port_enable(port_t port) {
	if (port == PortA) RCC->IOPENR |= RCC_IOPENR_IOPAEN;
	if (port == PortB) RCC->IOPENR |= RCC_IOPENR_IOPBEN;
	if (port == PortC) RCC->IOPENR |= RCC_IOPENR_IOPCEN;
	if (port == PortD) RCC->IOPENR |= RCC_IOPENR_IOPDEN;
}

void pin_mode(pin_t pin, pin_mode_t mode) {
	port_enable(pin_port(pin));
	gpio_t * gpio = GPIO(pin_port(pin));
	switch (mode) {
		case InputFloat:
			gpio_mode(pin, INPUT);
			gpio_pull(pin, NO_PULL);
			break;
		case InputPullUp:
			gpio_mode(pin, INPUT);
			gpio_pull(pin, PULL_UP);
			break;
		case InputPullDown:
			gpio_mode(pin, INPUT);
			gpio_pull(pin, PULL_DOWN);
			break;
		case InputAnalog:
			gpio_mode(pin, ANALOG);
			gpio_pull(pin, NO_PULL);
			break;
		case OutputPushPull:
			gpio_mode(pin, OUTPUT);
			gpio_otype(pin, PUSH_PULL);
			gpio_ospeed(pin, HIGH_SPEED);
			break;
		case OutputOpenDrain:
			gpio_mode(pin, OUTPUT);
			gpio_otype(pin, OPEN_DRAIN);
			break;
		case AlternateOutputPushPull:
			gpio_mode(pin, ALTERNATE);
			gpio_otype(pin, PUSH_PULL);
			break;
		case AlternateOutputOpenDrain:
			gpio_mode(pin, ALTERNATE);
			gpio_otype(pin, OPEN_DRAIN);
			break;
	}
}

void pin_set(pin_t pin) {
	gpio_t * gpio = GPIO(pin_port(pin));
	gpio->BSRR |= pin_mask(pin);
}

void pin_reset(pin_t pin) {
	gpio_t * gpio = GPIO(pin_port(pin));
	gpio->BRR = pin_mask(pin);
}

void pin_write(pin_t pin, bool state) {
	if (state)
		pin_set(pin);
	else
		pin_reset(pin);
}

void port_low_byte_mode(port_t port, pin_mode_t mode) {
	port_enable(port);
	for (int i; i < 8; i++)
		pin_mode((pin_t)((port << 8) + i), mode);
}

void port_high_byte_mode(port_t port, pin_mode_t mode) {
	port_enable(port);
	for (int i = 8; i < 16; i++)
		pin_mode((pin_t)((port << 8) + i), mode);
}

void port_mode(port_t port, pin_mode_t mode) {
	port_low_byte_mode(port, mode);
}

void port_write_word(port_t port, uint16_t value) {
	GPIO(port)->ODR = value;
}

void port_write_low_byte(port_t port, uint8_t value) {
	GPIO(port)->BSRR = value | (~value << 16);
}

void port_write_high_byte(port_t port, uint8_t value) {
	GPIO(port)->BSRR = (value < 8) | (~value << 24);
}

void port_write_byte(port_t port, uint8_t value) {
	port_write_low_byte(port, value);
}

uint8_t port_read_low_byte(port_t port) {
	return GPIO(port)->IDR & 0xFF;
}

uint8_t port_read_high_byte(port_t port) {
	return GPIO(port)->IDR >> 8;
}

uint8_t port_read_byte(port_t port) {
	return port_read_low_byte(port);
}



gpio.l0.c

#ifndef _gpio_h
#define _gpio_h
#include <stdint.h>
#include <stdbool.h>

typedef enum {
	PortA = 0,
	PortB = 1,
	PortC = 2,
	PortD = 3,
} port_t;

typedef enum {
	PinA0  = 0x0000,
	PinA1  = 0x0001,
	PinA2  = 0x0002,
	PinA3  = 0x0003,
	PinA4  = 0x0004,
	PinA5  = 0x0005,
	PinA6  = 0x0006,
	PinA7  = 0x0007,
	PinA8  = 0x0008,
	PinA9  = 0x0009,
	PinA10 = 0x000A,
	PinA11 = 0x000B,
	PinA12 = 0x000C,
	PinA13 = 0x000D,
	PinA14 = 0x000E,
	PinA15 = 0x000F,
	PinB0  = 0x0100,
	PinB1  = 0x0101,
	PinB2  = 0x0102,
	PinB3  = 0x0103,
	PinB4  = 0x0104,
	PinB5  = 0x0105,
	PinB6  = 0x0106,
	PinB7  = 0x0107,
	PinB8  = 0x0108,
	PinB9  = 0x0109,
	PinB10 = 0x010A,
	PinB11 = 0x010B,
	PinB12 = 0x010C,
	PinB13 = 0x010D,
	PinB14 = 0x010E,
	PinB15 = 0x010F,
	PinC0  = 0x0200,
	PinC1  = 0x0201,
	PinC2  = 0x0202,
	PinC3  = 0x0203,
	PinC4  = 0x0204,
	PinC5  = 0x0205,
	PinC6  = 0x0206,
	PinC7  = 0x0207,
	PinC8  = 0x0208,
	PinC9  = 0x0209,
	PinC10 = 0x020A,
	PinC11 = 0x020B,
	PinC12 = 0x020C,
	PinC13 = 0x020D,
	PinC14 = 0x020E,
	PinC15 = 0x020F,
	PinD0  = 0x0300,
	PinD1  = 0x0301,
	PinD2  = 0x0302,
	PinD3  = 0x0303,
	PinD4  = 0x0304,
	PinD5  = 0x0305,
	PinD6  = 0x0306,
	PinD7  = 0x0307,
	PinD8  = 0x0308,
	PinD9  = 0x0309,
	PinD10 = 0x030A,
	PinD11 = 0x030B,
	PinD12 = 0x030C,
	PinD13 = 0x030D,
	PinD14 = 0x030E,
	PinD15 = 0x030F,
} pin_t;

typedef enum {
	InputFloat,
	InputPullUp,
	InputPullDown,
	InputAnalog,
	OutputPushPull,
	OutputOpenDrain,
	AlternateOutputOpenDrain,
	AlternateOutputPushPull,
	Input = InputFloat,
	Output = OutputPushPull,
	AlternateOutput = AlternateOutputOpenDrain,
} pin_mode_t;

#define pin_port(pin) ((port_t) (pin >> 8))
#define pin_number(pin) (pin & 0xFF)
#define pin_mask(pin) ((uint16_t)(1 << pin_number(pin)))
#define pin_mask2(pin) ((uint32_t)(3 << (2 * pin_number(pin))))

#ifdef __cplusplus
extern "C" {
#endif

void port_enable(port_t port);
void port_disable(port_t port);

void port_low_byte_mode(port_t port, pin_mode_t mode);
void port_high_byte_mode(port_t port, pin_mode_t mode);
void port_mode(port_t port, pin_mode_t mode);

void port_write_word(port_t port, uint16_t value);
void port_write_low_byte(port_t port, uint8_t value);
void port_write_high_byte(port_t port, uint8_t value);
void port_write_byte(port_t port, uint8_t value);

uint16_t port_read_word(port_t port);
uint8_t port_read_low_byte(port_t port);
uint8_t port_read_high_byte(port_t port);
uint8_t port_read_byte(port_t port);

void pin_mode(pin_t pin, pin_mode_t mode);
void pin_set(pin_t pin);
void pin_reset(pin_t pin);
void pin_write(pin_t pin, bool state);

#ifdef __cplusplus
}
#endif
#endif


gpio.h

#include "system.h"
#include "stm32l0x1.h"
#include <stdint.h>

extern uint32_t _etext, _sdata, _edata, _sbss, _ebss;

void reset_handler() {
	// copy .data from flash to ram
	uint32_t data_size = (uint32_t)&_edata - (uint32_t)&_sdata;
	uint8_t *flash_data = (uint8_t*) &_etext;
	uint8_t *sram_data = (uint8_t*) &_sdata;
	for (uint32_t i = 0; i < data_size; i++)
		sram_data[i] = flash_data[i];
	// zero-fill .bss section in ram
	uint32_t bss_size = (uint32_t)&_ebss - (uint32_t)&_sbss;
	uint32_t *bss = (uint32_t*) &_sbss;
	for (uint32_t i = 0; i < bss_size; i++)
		bss[i] = 0;

	// setup external 32Mhz clock
	FLASH->ACR |= FLASH_ACR_LATENCY |
                  //FLASH_ACR_PRFTEN |
                  //FLASH_ACR_PRE_READ);
	//FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY) | FLASH_ACR_LATENCY_ONE_WAIT_STATE; // 1 wait state

  RCC->CR    |=  (RCC_CR_HSI16ON);
  while (!(RCC->CR & RCC_CR_HSI16RDY)) {};
  // Configure the PLL to use HSI16 with a PLLDIV of 2 and PLLMUL of 4.
  RCC->CFGR  &= ~(RCC_CFGR_PLLDIV |
                  RCC_CFGR_PLLMUL |
                  RCC_CFGR_PLLSRC);
  RCC->CFGR  |=  (RCC_CFGR_PLLDIV_DIV2 |
                  RCC_CFGR_PLLMUL_MULL4 |
                  RCC_CFGR_PLLSRC_HSI16);
  // Enable the PLL and wait for it to stabilize.
  RCC->CR    |=  (RCC_CR_PLLON);
  while (!(RCC->CR & RCC_CR_PLLRDY)) {};


	//RCC->CR |= RCC_CR_HSEON; // enable hse
	//while (!(RCC->CR & RCC_CR_HSERDY));
	//RCC->CFGR |= RCC_CFGR_PLLSRC // HSE as PLL input
//		| RCC_CFGR_PPRE1_DIV2 // APB1 prescale 2 (<36MHz)
		//| RCC_CFGR_PLLMUL_MULL4; // clk = 8 * 4 = 32Mhz
	//RCC->CR |= RCC_CR_PLLON;
	//while (!(RCC->CR & RCC_CR_PLLRDY));
	//RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; // PLL as system clock source
	
	SYSTICK->RVR = 2099;
	SYSTICK->CVR = 0;
	SYSTICK->CSR = SYSTICK_CSR_ENABLE | SYSTICK_CSR_TICKINT;// | SYSTICK_CSR_CLKSOURCE;
	//RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
	
	// main
	setup();
	while (1)
		loop();
}

static volatile uint32_t _system_ticks;

void systick_handler() {
	_system_ticks++;
}

uint32_t system_ms() {
	return _system_ticks;
}

void delay_ms(uint32_t ms) {
	uint32_t start = system_ms();
	while (system_ms() < start + ms);
}

system.l0.c

#ifndef _system_h
#define _system_h
#include <stdint.h>

#ifdef __cplusplus
extern "C" {
#endif
uint32_t system_ms();
void delay_ms(uint32_t ms);
void setup();
void loop();
#ifdef __cplusplus
}
#endif
#endif


system.h

#include "hd44780.h"
#include "gpio.h"

typedef enum {
  CLEAR_DISPLAY = 0x01,
  RETURN_HOME = 0x02,
  ENTRY_MODE_SET = 0x04,
  DISPLAY_ON_OFF_CONTROL = 0x08,
  CURSOR_OR_DISPLAY_SHIFT = 0x10,
  FUNCTION_SET = 0x20,
  SET_CGRAM_ADDRESS = 0x40,
  SET_DDRAM_ADDRESS = 0x80,
} hd44780_command_t;

static pin_t _rs_pin;
static pin_t _rw_pin;
static pin_t _e_pin;
static port_t _data_port;

static void hd44780_write(uint8_t data, bool rs) {
  // TODO: delay
  pin_reset(_e_pin);
  pin_write(_rs_pin, rs);
  pin_reset(_rw_pin);
  port_mode(_data_port, Output);
  port_write_byte(_data_port, data);
  pin_set(_e_pin);
  pin_reset(_e_pin);
  pin_set(_rw_pin);
  port_mode(_data_port, Input);
  while (port_read_byte(_data_port) & 0x80);
}

static void hd44780_write_command(uint8_t command) {
  hd44780_write(command, false);
}

static void hd44780_write_data(uint8_t data) {
  hd44780_write(data, true);
}

void hd44780_enable(pin_t rs_pin, pin_t rw_pin, pin_t e_pin, port_t data_port) {
  _rs_pin = rs_pin;
  _rw_pin = rw_pin;
  _e_pin = e_pin;
  _data_port = data_port;
  pin_mode(_rs_pin, Output);
  pin_mode(_rw_pin, Output);
  pin_mode(_e_pin, Output);
  port_mode(_data_port, Output);
  hd44780_write_command(DISPLAY_ON_OFF_CONTROL + 4);
  hd44780_write_command(CLEAR_DISPLAY);
}

void hd44780_disable() {
  hd44780_write_command(DISPLAY_ON_OFF_CONTROL);
}

void hd44780_print(uint8_t x, uint8_t y, uint8_t * data) {
  uint8_t addr = (uint8_t[]){0, 64, 20, 84}[y] + x;
  hd44780_write_command(SET_DDRAM_ADDRESS + addr);
  uint8_t i = 0;
  while (data[i] != 0)
    hd44780_write_data(data[i++]);
}

hd44780.c

#ifndef _hd44780_h
#define _hd44780_h
#include "gpio.h"
#include <stdint.h>
#include <stdbool.h>

#ifdef __cplusplus
extern "C" {
#endif

void hd44780_enable(pin_t rs_pin, pin_t rw_pin, pin_t e_pin, port_t data_port);
void hd44780_disable();
void hd44780_print(uint8_t x, uint8_t y, uint8_t * data);

#ifdef __cplusplus
}
#endif
#endif


hd44780.h

#include "system.h"
#include "stm32l0x1.h"
#include "hd44780.h"

char * buf[10];
uint32_t stamp = 0;
uint16_t framecount = 0;
uint16_t fps = 0;

#define LED PinB3

void setup() {
	pin_mode(LED, OutputPushPull);
	pin_set(LED);
	return;
	hd44780_enable(PinD0, PinD1, PinD2, PortA);
}

void loop() {
	//return;
	if (system_ms() % 1000 < 500)
		pin_set(LED);
	else
		pin_reset(LED);
	return;

	uint32_t now = system_ms();
	if (now % 1000 < stamp % 1000) {
		fps = framecount;
		framecount = 0;
	}
	stamp = now;
	framecount++;
	sprintf(&buf, "time: %05lu", system_ms());
	hd44780_print(0, 0, buf);
	sprintf(&buf, "FPS: %u", fps);
	hd44780_print(0, 1, buf);


}


demo.c

#include <stdint.h>

void default_handler() {
	while(1);
};

void reset_handler(void) __attribute__((weak, alias("default_handler")));
void nmi_handler(void) __attribute__((weak, alias("default_handler")));
void hard_fault_handler(void) __attribute__((weak, alias("default_handler")));
void svc_handler(void) __attribute__((weak, alias("default_handler")));
void pendsv_handler(void) __attribute__((weak, alias("default_handler")));
void systick_handler(void) __attribute__((weak, alias("default_handler")));
void wwdg_handler(void) __attribute__((weak, alias("default_handler")));
void pvd_handler(void) __attribute__((weak, alias("default_handler")));
void rtc_handler(void) __attribute__((weak, alias("default_handler")));
void flash_handler(void) __attribute__((weak, alias("default_handler")));
void rcc_handler(void) __attribute__((weak, alias("default_handler")));
void exti0_1_handler(void) __attribute__((weak, alias("default_handler")));
void exti2_3_handler(void) __attribute__((weak, alias("default_handler")));
void exti4_15_handler(void) __attribute__((weak, alias("default_handler")));
void dma1_channel1_handler(void) __attribute__((weak, alias("default_handler")));
void dma1_channel2_3_handler(void) __attribute__((weak, alias("default_handler")));
void dma1_channel4_7_handler(void) __attribute__((weak, alias("default_handler")));
void adc_comp_handler(void) __attribute__((weak, alias("default_handler")));
void lptim1_handler(void) __attribute__((weak, alias("default_handler")));
void usart4_5_handler(void) __attribute__((weak, alias("default_handler")));
void tim2_handler(void) __attribute__((weak, alias("default_handler")));
void tim3_handler(void) __attribute__((weak, alias("default_handler")));
void tim6_handler(void) __attribute__((weak, alias("default_handler")));
void tim7_handler(void) __attribute__((weak, alias("default_handler")));
void tim21_handler(void) __attribute__((weak, alias("default_handler")));
void i2c3_handler(void) __attribute__((weak, alias("default_handler")));
void tim22_handler(void) __attribute__((weak, alias("default_handler")));
void i2c1_handler(void) __attribute__((weak, alias("default_handler")));
void i2c2_handler(void) __attribute__((weak, alias("default_handler")));
void spi1_handler(void) __attribute__((weak, alias("default_handler")));
void spi2_handler(void) __attribute__((weak, alias("default_handler")));
void usart1_handler(void) __attribute__((weak, alias("default_handler")));
void usart2_handler(void) __attribute__((weak, alias("default_handler")));
void lpuart_aes_handler(void) __attribute__((weak, alias("default_handler")));

uint32_t isr_vector[48] __attribute__((section(".isr_vector"))) = {
	0x200017FF, // stack pointer
	(uint32_t)&reset_handler,
	(uint32_t)&nmi_handler,
	(uint32_t)&hard_fault_handler,
	0,
	0,
	0,
	0,
	0,
	0,
	0,
	(uint32_t)&svc_handler,
	0,
	0,
	(uint32_t)&pendsv_handler,
	(uint32_t)&systick_handler,
	(uint32_t)&wwdg_handler, // 0x40
	(uint32_t)&pvd_handler, // 0x44
	(uint32_t)&rtc_handler, // 0x48
	(uint32_t)&flash_handler, // 0x4c
	(uint32_t)&rcc_handler, // 0x50
	(uint32_t)&exti0_1_handler, // 0x54
	(uint32_t)&exti2_3_handler, // 0x58
	(uint32_t)&exti4_15_handler, // 0x5c
	0,
	(uint32_t)&dma1_channel1_handler, // 0x64
	(uint32_t)&dma1_channel2_3_handler, // 0x68
	(uint32_t)&dma1_channel4_7_handler, // 0x6c
	(uint32_t)&adc_comp_handler, // 0x70
	(uint32_t)&lptim1_handler, // 0x74
	(uint32_t)&usart4_5_handler, // 0x78
	(uint32_t)&tim2_handler, // 0x7c
	(uint32_t)&tim3_handler, // 0x80
	(uint32_t)&tim6_handler, // 0x84
	(uint32_t)&tim7_handler, // 0x88
	0,
	(uint32_t)&tim21_handler, // 0x90
	(uint32_t)&i2c3_handler, // 0x94
	(uint32_t)&tim22_handler, // 0x98
	(uint32_t)&i2c1_handler, // 0x9c
	(uint32_t)&i2c2_handler, // 0xa0
	(uint32_t)&spi1_handler, // 0xa4
	(uint32_t)&spi2_handler, // 0xa8
	(uint32_t)&usart1_handler, // 0xac
	(uint32_t)&usart2_handler, // 0xb0
	(uint32_t)&lpuart_aes_handler, // 0xb4
	0,
	0
};


stm32l0x1.c

#ifndef stm32l0x1_h
#define stm32l0x1_h
#include <stdint.h>

////////////////////////////////////////
// FLASH memory (page 114)
////////////////////////////////////////

typedef volatile struct {
  uint32_t ACR;			 // access control register
  uint32_t PECR;
  uint32_t PDKEYR;
  uint32_t PKEYR;
  uint32_t PRGKEYR;
  uint32_t OPTKEYR;			 // option key register
  uint32_t SR;			 // status register
  uint32_t OPTR;			 // option control register
  uint32_t WRPROT1;
  uint32_t WRPROT2;
} flash_t;

typedef enum {
  FLASH_ACR_LATENCY = 0x00000001,
    FLASH_ACR_LATENCY_NO_WAIT_STATES = 0x00000000,			 // clk <= 24Mhz
    FLASH_ACR_LATENCY_ONE_WAIT_STATE = 0x00000001,			 // clk > 24Mhz
  FLASH_ACR_PRFTEN = 0x00000002,			 // prefetch enable
  FLASH_ACR_SLEEP_PD = 0x00000008,
  FLASH_ACR_RN_PD = 0x00000010,
  FLASH_ACR_DESAB8_BUF = 0x00000020,
  FLASH_ACR_PRE_READ = 0x00000040,
} flash_acr_t;

typedef enum {
  FLASH_PECR_PELOCK = 0x00000001,
  FLASH_PECR_PRGLOCK = 0x00000002,
  FLASH_PECR_OPTLOCK = 0x00000004,
  FLASH_PECR_PRG = 0x00000008,
  FLASH_PECR_DATA = 0x00000010,
  FLASH_PECR_FIX = 0x00000100,
  FLASH_PECR_ERASE = 0x00000200,
  FLASH_PECR_FPRG = 0x00000400,
  FLASH_PECR_PARALLELBANK = 0x00008000,
  FLASH_PECR_EOPIE = 0x00010000,
  FLASH_PECR_ERRIE = 0x00020000,
  FLASH_PECR_OBL_LAUNCH = 0x00040000,
  FLASH_PECR_NZDISABLE = 0x00800000,
} flash_pecr_t;

typedef enum {
  FLASH_SR_BSY = 0x00000001,
  FLASH_SR_EOP = 0x00000002,
  FLASH_SR_ENDHV = 0x00000004,
  FLASH_SR_READY = 0x00000008,
  FLASH_SR_WRPERR = 0x00000100,
  FLASH_SR_PGAERR = 0x00000200,
  FLASH_SR_SIZERR = 0x00000400,
  FLASH_SR_OPTVERR = 0x00000800,
  FLASH_SR_RDERR = 0x00002000,
  FLASH_SR_NOTZEROERR = 0x00010000,
  FLASH_SR_FWWERR = 0x00020000,
} flash_sr_t;

typedef enum {
  FLASH_OPTR_RDPROT = 0x000000FF,
  FLASH_OPTR_WPRMOD = 0x00000100,
  FLASH_OPTR_BOR_LEV = 0x000F0000,
  FLASH_OPTR_WDG_SW = 0x00100000,
  FLASH_OPTR_nRST_STOP = 0x00200000,
  FLASH_OPTR_nRST_STBY = 0x00400000,
  FLASH_OPTR_BFB2 = 0x00800000,
  FLASH_OPTR_nBOOT_SEL = 0x20000000,
  FLASH_OPTR_nBOOT0 = 0x40000000,
  FLASH_OPTR_nBOOT1 = 0x80000000,
} flash_optr_t;

////////////////////////////////////////
// RCC - reset and clock control (page 213)
////////////////////////////////////////

typedef volatile struct {
  uint32_t CR;			 // control register
  uint32_t ICSCR;
  uint32_t CFGR;			 // configuration register
  uint32_t CIER;
  uint32_t CIFR;
  uint32_t CICR;
  uint32_t IOPRSTR;
  uint32_t AHBRSTR;
  uint32_t APB2RSTR;
  uint32_t APB1RSTR;
  uint32_t IOPENR;			 // i/o port enable register
  uint32_t AHBENR;
  uint32_t APB2ENR;
  uint32_t APB1ENR;
  uint32_t IOPSMENR;
  uint32_t AHBSMENR;
  uint32_t APB2SMENR;
  uint32_t APB1SMENR;
  uint32_t CCIPR;
  uint32_t CSR;
} rcc_t;

typedef enum {
  RCC_CR_HSI16ON = 0x00000001,
  RCC_CR_HSI16KERON = 0x00000002,
  RCC_CR_HSI16RDYF = 0x00000004,
  RCC_CR_HSI16DIVEN = 0x00000008,
  RCC_CR_HSI16DIVF = 0x00000010,
  RCC_CR_HSI16OUTEN = 0x00000020,
  RCC_CR_MSION = 0x00000100,
  RCC_CR_MSIRDY = 0x00000200,
  RCC_CR_HSEON = 0x00010000,			 // high speed external osc on
  RCC_CR_HSERDY = 0x00020000,			 // high speed external osc ready
  RCC_CR_HSEBYP = 0x00040000,
  RCC_CR_CSSHSEON = 0x00080000,
  RCC_CR_RTCPRE = 0x00300000,
    RCC_CR_RTCPRE_DIV2 = 0x00000000,
    RCC_CR_RTCPRE_DIV4 = 0x00100000,
    RCC_CR_RTCPRE_DIV8 = 0x00200000,
    RCC_CR_RTCPRE_DIV16 = 0x00300000,
  RCC_CR_PLLON = 0x01000000,
  RCC_CR_PLLRDY = 0x02000000,
} rcc_cr_t;

typedef enum {
  RCC_CFGR_SW = 0x00000003,			 // clock source
    RCC_CFGR_SW_MSI = 0x00000000,
    RCC_CFGR_SW_HSI16 = 0x00000001,
    RCC_CFGR_SW_HSE = 0x00000002,
    RCC_CFGR_SW_PLL = 0x00000003,
  RCC_CFGR_SWS = 0x0000000C,			 // selected clock source
    RCC_CFGR_SWS_MSI = 0x00000000,
    RCC_CFGR_SWS_HSI16 = 0x00000004,
    RCC_CFGR_SWS_HSE = 0x00000008,
    RCC_CFGR_SWS_PLL = 0x0000000c,
  RCC_CFGR_HPRE = 0x000000F0,
    RCC_CFGR_HPRE_DIV1 = 0x00000000,
    RCC_CFGR_HPRE_DIV2 = 0x00000080,
    RCC_CFGR_HPRE_DIV4 = 0x00000090,
    RCC_CFGR_HPRE_DIV8 = 0x000000a0,
    RCC_CFGR_HPRE_DIV16 = 0x000000b0,
    RCC_CFGR_HPRE_DIV64 = 0x000000c0,
    RCC_CFGR_HPRE_DIV128 = 0x000000d0,
    RCC_CFGR_HPRE_DIV256 = 0x000000e0,
    RCC_CFGR_HPRE_DIV512 = 0x000000f0,
  RCC_CFGR_PPRE1 = 0x00000700,			 // peripheral prescaler
    RCC_CFGR_PPRE1_DIV1 = 0x00000000,			 // clk
    RCC_CFGR_PPRE1_DIV2 = 0x00000400,			 // clk/2
    RCC_CFGR_PPRE1_DIV4 = 0x00000500,			 // clk/4
    RCC_CFGR_PPRE1_DIV8 = 0x00000600,			 // clk/8
    RCC_CFGR_PPRE1_DIV16 = 0x00000700,			 // clk/16
  RCC_CFGR_STOPWUCK = 0x00001000,
  RCC_CFGR_PLLSRC = 0x00002000,
    RCC_CFGR_PLLSRC_HSI16 = 0x00000000,
    RCC_CFGR_PLLSRC_HSE = 0x00002000,
  RCC_CFGR_PLLMUL = 0x00078000,
    RCC_CFGR_PLLMUL_MULL3 = 0x00000000,
    RCC_CFGR_PLLMUL_MULL4 = 0x00008000,
    RCC_CFGR_PLLMUL_MULL6 = 0x00010000,
    RCC_CFGR_PLLMUL_MULL8 = 0x00018000,
    RCC_CFGR_PLLMUL_MULL12 = 0x00020000,
    RCC_CFGR_PLLMUL_MULL16 = 0x00028000,
    RCC_CFGR_PLLMUL_MULL24 = 0x00030000,
    RCC_CFGR_PLLMUL_MULL32 = 0x00038000,
    RCC_CFGR_PLLMUL_MULL48 = 0x00040000,
  RCC_CFGR_PLLDIV = 0x00180000,
    RCC_CFGR_PLLDIV_DIV2 = 0x00080000,
    RCC_CFGR_PLLDIV_DIV3 = 0x00100000,
    RCC_CFGR_PLLDIV_DIV4 = 0x00180000,
  RCC_CFGR_MCOSEL = 0x00E00000,
  RCC_CFGR_MCOPRE = 0x0E000000,
} rcc_cfgr_t;

typedef enum {
  RCC_CIER_LSIRDYIE = 0x00000001,
  RCC_CIER_LSERDYIE = 0x00000002,
  RCC_CIER_HSI16RDYIE = 0x00000004,
  RCC_CIER_HSERDYIE = 0x00000008,
  RCC_CIER_PLLRDYIE = 0x00000010,
  RCC_CIER_MSIRDYIE = 0x00000020,
  RCC_CIER_CSSLSE = 0x00000080,
} rcc_cier_t;

typedef enum {
  RCC_CIFR_LSIRDYF = 0x00000001,
  RCC_CIFR_LSERDYF = 0x00000002,
  RCC_CIFR_HSI16RDYF = 0x00000004,
  RCC_CIFR_HSERDYF = 0x00000008,
  RCC_CIFR_PLLRDYF = 0x00000010,
  RCC_CIFR_MSIRDYF = 0x00000020,
  RCC_CIFR_CSSLSEF = 0x00000080,
  RCC_CIFR_CSSHSEF = 0x00000100,
} rcc_cifr_t;

typedef enum {
  RCC_CICR_LSIRDYC = 0x00000001,
  RCC_CICR_LSERDYC = 0x00000002,
  RCC_CICR_HSI16RDYC = 0x00000004,
  RCC_CICR_HSERDYC = 0x00000008,
  RCC_CICR_PLLRDYC = 0x00000010,
  RCC_CICR_MSIRDYC = 0x00000020,
  RCC_CICR_CSSLSEC = 0x00000080,
  RCC_CICR_CSSHSEC = 0x00000100,
} rcc_cicr_t;

typedef enum {
  RCC_IOPRSTR_IOPARST = 0x00000001,
  RCC_IOPRSTR_IOPBRST = 0x00000002,
  RCC_IOPRSTR_IOPCRST = 0x00000004,
  RCC_IOPRSTR_IOPDRST = 0x00000008,
  RCC_IOPRSTR_IOPERST = 0x00000010,
  RCC_IOPRSTR_IOPHRST = 0x00000080,
} rcc_ioprstr_t;

typedef enum {
  RCC_AHBRSTR_DMARST = 0x00000001,
  RCC_AHBRSTR_MIFRST = 0x00000100,
  RCC_AHBRSTR_CRCRST = 0x00001000,
  RCC_AHBRSTR_CRYPRST = 0x01000000,
} rcc_ahbrstr_t;

typedef enum {
  RCC_APB2RSTR_SYSCFGRST = 0x00000001,
  RCC_APB2RSTR_TIM21RST = 0x00000004,
  RCC_APB2RSTR_TM12RST = 0x00000020,
  RCC_APB2RSTR_ADCRST = 0x00000200,
  RCC_APB2RSTR_USART1RST = 0x00001000,
  RCC_APB2RSTR_DBGRST = 0x00100000,
} rcc_apb2rstr_t;

typedef enum {
  RCC_APB1RSTR_TIM2RST = 0x00000001,
  RCC_APB1RSTR_TIM3RST = 0x00000002,
  RCC_APB1RSTR_TIM6RST = 0x00000010,
  RCC_APB1RSTR_TIM7RST = 0x00000020,
  RCC_APB1RSTR_WWDRST = 0x00000800,
  RCC_APB1RSTR_SPI2RST = 0x00004000,
  RCC_APB1RSTR_USART2RST = 0x00020000,
  RCC_APB1RSTR_LPUART2RST = 0x00040000,
  RCC_APB1RSTR_USART4RST = 0x00080000,
  RCC_APB1RSTR_USART5RST = 0x00100000,
  RCC_APB1RSTR_I2C1RST = 0x00200000,
  RCC_APB1RSTR_I2C2RST = 0x00400000,
  RCC_APB1RSTR_PWRRST = 0x10000000,
  RCC_APB1RSTR_I2C3RST = 0x40000000,
  RCC_APB1RSTR_LPTIM1RST = 0x80000000,
} rcc_apb1rstr_t;

typedef enum {
  RCC_IOPENR_IOPAEN = 0x00000001,			 // gpio A enable
  RCC_IOPENR_IOPBEN = 0x00000002,			 // gpio B enable
  RCC_IOPENR_IOPCEN = 0x00000004,			 // gpio C enable
  RCC_IOPENR_IOPDEN = 0x00000008,			 // gpio D enable
  RCC_IOPENR_IOPFEN = 0x00000010,			 // gpio E enable
  RCC_IOPENR_IOPHEN = 0x00000080,			 // gpio H enable
} rcc_iopenr_t;

typedef enum {
  RCC_AHBENR_DMAEN = 0x00000001,
  RCC_AHBENR_MIFEN = 0x00000100,
  RCC_AHBENR_C = 0x00000E00,
  RCC_AHBENR_CRCEN = 0x00001000,
  RCC_AHBENR_CRYPEN = 0x01000000,
} rcc_ahbenr_t;

typedef enum {
  RCC_APB2ENR_SYSCFGEN = 0x00000001,
  RCC_APB2ENR_TIM21EN = 0x00000004,
  RCC_APB2ENR_TIM22EN = 0x00000020,
  RCC_APB2ENR_FWEN = 0x00000080,
  RCC_APB2ENR_ADCEN = 0x00000200,
  RCC_APB2ENR_SPI1EN = 0x00001000,
  RCC_APB2ENR_USART1EN = 0x00004000,
  RCC_APB2ENR_DBGEN = 0x00400000,
} rcc_apb2enr_t;

typedef enum {
  RCC_APB1ENR_TIM2EN = 0x00000001,
  RCC_APB1ENR_TIM3EN = 0x00000002,
  RCC_APB1ENR_TIM6EN = 0x00000010,
  RCC_APB1ENR_TIM7EN = 0x00000020,
  RCC_APB1ENR_WWDGEN = 0x00000800,
  RCC_APB1ENR_SPI2EN = 0x00004000,
  RCC_APB1ENR_USART2EN = 0x00020000,
  RCC_APB1ENR_LPUART1EN = 0x00040000,
  RCC_APB1ENR_USART4EN = 0x00080000,
  RCC_APB1ENR_USART5EN = 0x00100000,
  RCC_APB1ENR_I2C1EN = 0x00200000,
  RCC_APB1ENR_I2C2EN = 0x00400000,
  RCC_APB1ENR_PWREN = 0x10000000,
  RCC_APB1ENR_I2C3EN = 0x40000000,
  RCC_APB1ENR_LPTIM1EM = 0x80000000,
} rcc_apb1enr_t;

typedef enum {
  RCC_CSR_LSION = 0x00000001,
  RCC_CSR_LSIRDY = 0x00000002,
  RCC_CSR_LSEON = 0x00000100,
  RCC_CSR_LERDY = 0x00000200,
  RCC_CSR_RSEBYBP = 0x00000400,
  RCC_CSR_LSEDRV = 0x00001800,
  RCC_CSR_CSSLSEON = 0x00002000,
  RCC_CSR_CSSLSED = 0x00004000,
  RCC_CSR_RTCSEL = 0x00030000,
  RCC_CSR_RTCEN = 0x00040000,
  RCC_CSR_RTCRST = 0x00080000,
  RCC_CSR_RMVF = 0x00800000,
  RCC_CSR_FWRSTF = 0x01000000,
  RCC_CSR_OBLRSTF = 0x02000000,
  RCC_CSR_PINRSTF = 0x04000000,
  RCC_CSR_PORRSTF = 0x08000000,
  RCC_CSR_SFTRSTF = 0x10000000,
  RCC_CSR_IWDGRSTF = 0x20000000,
  RCC_CSR_WWDGRSTF = 0x40000000,
  RCC_CSR_LPWRSTF = 0x80000000,
} rcc_csr_t;

////////////////////////////////////////
// GPIO (page 231)
////////////////////////////////////////

typedef volatile struct {
  uint32_t MODER;			 // mode register
  uint32_t OTYPER;			 // output type register
  uint32_t OSPEEDR;			 // output speed register
  uint32_t PUPDR;			 // pull up/down register
  uint32_t IDR;			 // input data register
  uint32_t ODR;			 // output data register
  uint32_t BSRR;			 // bit set/reset register
  uint32_t LCKR;			 // lock register
  uint32_t AFRL;			 // alternate function register low
  uint32_t AFRH;			 // alternate function register high
  uint32_t BRR;			 // bit reset register
} gpio_t;

////////////////////////////////////////
// SPI (page 803)
////////////////////////////////////////

typedef volatile struct {
  uint32_t CR1;			 // contol register 1
  uint32_t CR2;			 // control register 2
  uint32_t SR;			 // status register
  uint32_t DR;			 // data register
  uint32_t CRCPR;			 // crc polynomial register
  uint32_t RXCRCR;			 // rx crc register
  uint32_t TXCRCR;			 // tx crc register
  uint32_t I2SCFGR;			 // i2s configuration register
  uint32_t I2SPR;			 // i2s prescaler register
} spi_t;

typedef enum {
  SPI_CR1_CPHA = 0x00000001,			 // clock phase
  SPI_CR1_CPOL = 0x00000002,			 // clock polarity
  SPI_CR1_MSTR = 0x00000004,			 // master selection
  SPI_CR1_BR = 0x00000038,			 // baud rate
    SPI_CR1_BR_DIV2 = 0x00000000,			 // clk/2
    SPI_CR1_BR_DIV4 = 0x00000008,			 // clk/4
    SPI_CR1_BR_DIV8 = 0x00000010,			 // clk/8
    SPI_CR1_BR_DIV16 = 0x00000018,			 // clk/16
    SPI_CR1_BR_DIV32 = 0x00000020,			 // clk/32
    SPI_CR1_BR_DIV64 = 0x00000028,			 // clk/64
    SPI_CR1_BR_DIV128 = 0x00000030,			 // clk/126
    SPI_CR1_BR_DIV256 = 0x00000038,			 // clk/256
  SPI_CR1_SPE = 0x00000040,			 // spi enable
  SPI_CR1_LSBFIRST = 0x00000080,			 // frame format
  SPI_CR1_SSI = 0x00000100,			 // internal slave select
  SPI_CR1_SSM = 0x00000200,			 // software slave mamagement
  SPI_CR1_RXONLY = 0x00000400,			 // receive only
  SPI_CR1_CRCL = 0x00000800,			 // crc length
  SPI_CR1_CRCNEXT = 0x00001000,			 // crc next
  SPI_CR1_CRCEN = 0x00002000,			 // crc enable
  SPI_CR1_BIDIOE = 0x00004000,			 // bidirectional output enable
  SPI_CR1_BIDIMODE = 0x00008000,			 // bidirectional mode
} spi_cr1_t;

typedef enum {
  SPI_CR2_RXDMAEN = 0x00000001,			 // rx DMA enable
  SPI_CR2_TXDMAEN = 0x00000002,			 // tx DMA enable
  SPI_CR2_SSOE = 0x00000004,			 // SS output enable
  SPI_CR2_NSSP = 0x00000008,			 // NSS pulse
  SPI_CR2_FRF = 0x00000010,			 // frame format
    SPI_CR2_FRF_MOTOROLA = 0x00000000,
    SPI_CR2_FRF_TI = 0x00000010,
  SPI_CR2_ERRIE = 0x00000020,			 // error interrup enable
  SPI_CR2_RXNEIE = 0x00000040,			 // rx not empty interrupt enable
  SPI_CR2_TXEIE = 0x00000080,			 // tx empty interrupt enable
  SPI_CR2_DS = 0x00000F00,			 // data size
    SPI_CR2_DS_4BIT = 0x00000300,
    SPI_CR2_DS_5BIT = 0x00000400,
    SPI_CR2_DS_6BIT = 0x00000500,
    SPI_CR2_DS_7BIT = 0x00000600,
    SPI_CR2_DS_8BIT = 0x00000700,
    SPI_CR2_DS_9BIT = 0x00000800,
    SPI_CR2_DS_10BIT = 0x00000900,
    SPI_CR2_DS_11BIT = 0x00000a00,
    SPI_CR2_DS_12BIT = 0x00000b00,
    SPI_CR2_DS_13BIT = 0x00000c00,
    SPI_CR2_DS_14BIT = 0x00000d00,
    SPI_CR2_DS_15BIT = 0x00000e00,
    SPI_CR2_DS_16BIT = 0x00000f00,
  SPI_CR2_FRXTH = 0x00001000,			 // FIFO rx threshold
  SPI_CR2_LDMA_RX = 0x00002000,			 // last DMA rx
  SPI_CR2_LDMA_TX = 0x00004000,			 // last DMA tx
} spi_cr2_t;

typedef enum {
  SPI_SR_RXNE = 0x00000001,			 // rx buffer not empty
  SPI_SR_TXE = 0x00000002,			 // tx buffer empty
  SPI_SR_CHSIDE = 0x00000004,			 // channel side
  SPI_SR_UDR = 0x00000008,			 // underrun
  SPI_SR_CRCERR = 0x00000010,			 // crc error
  SPI_SR_MODF = 0x00000020,			 // mode fault
  SPI_SR_OVR = 0x00000040,			 // overrrun
  SPI_SR_BSY = 0x00000080,			 // busy
  SPI_SR_FRE = 0x00000100,			 // frame format error
  SPI_SR_FRLVL = 0x00000600,			 // FIFO rx level
    SPI_SR_FRLVL_EMPTY = 0x00000000,
    SPI_SR_FRLVL_QUARTER = 0x00000200,
    SPI_SR_FRLVL_HALF = 0x00000400,
    SPI_SR_FRLVL_FULL = 0x00000600,
  SPI_SR_FTLVL = 0x00001800,			 // FIFO tx level
    SPI_SR_FTLVL_EMPTY = 0x00000000,
    SPI_SR_FTLVL_QUARTER = 0x00000800,
    SPI_SR_FTLVL_HALF = 0x00001000,
    SPI_SR_FTLVL_FULL = 0x00001800,
} spi_sr_t;

typedef enum {
  SPI_I2SCFGR_CHLEN = 0x00000001,
  SPI_I2SCFGR_DATLEN = 0x00000006,
  SPI_I2SCFGR_CKPOL = 0x00000008,
  SPI_I2SCFGR_I2SSTD = 0x00000010,
  SPI_I2SCFGR_PCMSYNC = 0x00000040,
  SPI_I2SCFGR_ISCFG = 0x00000180,
  SPI_I2SCFGR_I2SE = 0x00000200,
  SPI_I2SCFGR_I2SMOD = 0x00000400,
  SPI_I2SCFGR_ASTREN = 0x00000800,
} spi_i2scfgr_t;

typedef enum {
  SPI_I2SPR_I2SDIV = 0x000000FF,
  SPI_I2SPR_ODD = 0x00000100,
  SPI_I2SPR_MCKOE = 0x00000200,
} spi_i2spr_t;

////////////////////////////////////////
// SYSTICK timer
////////////////////////////////////////

typedef volatile struct {
  uint32_t CSR;
  uint32_t RVR;
  uint32_t CVR;
  uint32_t CALIB;
} systick_t;

typedef enum {
  SYSTICK_CSR_ENABLE = 0x00000001,
  SYSTICK_CSR_TICKINT = 0x00000002,
  SYSTICK_CSR_CLKSOURCE = 0x00000004,
  SYSTICK_CSR_COUNTFLAG = 0x00010000,
} systick_csr_t;

#define FLASH ((flash_t *)(0x40022000))
#define RCC ((rcc_t *)(0x40021000))
#define GPIO(x) ((gpio_t *)(0x50000000 + 1024 * x))
#define SPI ((spi_t *)(0x40013000))
#define SYSTICK ((systick_t *)(0xE000E010))

#endif
