### Description

This circuit will output a string of inverted characters ('tiny tapeout') to the 7-segment display.

The logic to light the characters appears in the bottom half of the simulation window.

The top half of the simulation window implements a modulo-11 counter. In other words, the counter increments up to 11 then resets. This counter is used to determine which character we should output to the 7-segment display.

The truth table for the design can be found in the [Design Spreadsheet](https://docs.google.com/spreadsheets/d/1-h9pBYtuxv6su2EC8qBc6nX_JqHXks6Gx5nmHFQh_30/edit?usp=sharing)

| SW      | Function        | 
|---------|-----------------|
| 1       | N/A             | 
| 2       | Reset           | 
| 3       | N/A             |
| 4       | Clock Disable   | 
| 5       | A               | 
| 6       | B               |
| 7       | C               | 
| 8       | D               | 


Design [inspired by Rakesh Peter's tt01 submission](https://github.com/r4d10n/tinytapeout-HELLo-3orLd-7seg)
and re-inspired by the demo tutorial and previous tt06 submissions
gate53:IN
gate53:OUT
gate54:IN
gate54:OUT
gate55:IN
gate55:OUT
gate56:IN
gate56:OUT
gate57:IN
gate57:OUT
gate58:IN
gate58:OUT
gate59:IN
gate59:OUT
gate60:IN
gate60:OUT
A
!A
B
!B
C
!C
D
!D
gate61:A
gate61:B
gate61:OUT
gate74:A
gate74:B
gate74:OUT
gate75:A
gate75:B
gate75:OUT
gate76:A
gate76:B
gate76:OUT
gate77:A
gate77:B
gate77:OUT
gate78:A
gate78:B
gate78:OUT
A'BC + AB'C'D'
sw3:1a
sw3:2a
sw3:3a
sw3:4a
sw3:5a
sw3:6a
sw3:7a
sw3:8a
sw3:8b
sw3:7b
sw3:6b
sw3:5b
sw3:4b
sw3:3b
sw3:2b
sw3:1b
1
clock2:CLK
pwr9:VCC
Loading
tt-block-input
sw4:1
sw4:2
sw4:3
btn2:1.l
btn2:2.l
btn2:1.r
btn2:2.r
pwr10:VCC
pwr11:GND
led2:A
led2:C
pwr12:GND
led3:A
led3:C
gate79:A
gate79:B
gate79:OUT
gate80:A
gate80:B
gate80:OUT
A'BC
gate81:A
gate81:B
gate81:OUT
gate82:A
gate82:B
gate82:OUT
pwr13:GND
led5:A
led5:C
A'BC + A'CD + AB'C'D'
pwr14:GND
Loading
tt-block-output
sevseg1:COM.1
sevseg1:COM.2
sevseg1:A
sevseg1:B
sevseg1:C
sevseg1:D
sevseg1:E
sevseg1:F
sevseg1:G
sevseg1:DP
gate83:A
gate83:B
gate83:OUT
gate84:A
gate84:B
gate84:OUT
gate87:A
gate87:B
gate87:OUT
gate88:A
gate88:B
gate88:OUT
gate89:A
gate89:B
gate89:OUT
gate90:A
gate90:B
gate90:OUT
gate91:A
gate91:B
gate91:OUT
gate92:A
gate92:B
gate92:OUT
gate93:A
gate93:B
gate93:OUT
gate85:A
gate85:B
gate85:OUT
gate86:A
gate86:B
gate86:OUT
pwr15:GND
led6:A
led6:C
A'B'C + B'CD' + A'CD' + AB'C'D
gate94:A
gate94:B
gate94:OUT
gate95:A
gate95:B
gate95:OUT
gate96:A
gate96:B
gate96:OUT
gate97:A
gate97:B
gate97:OUT
gate98:A
gate98:B
gate98:OUT
gate99:A
gate99:B
gate99:OUT
gate100:A
gate100:B
gate100:OUT
gate101:IN
gate101:OUT
gate102:A
gate102:B
gate102:OUT
pwr16:GND
led7:A
led7:C
A'B'C + B'CD' + A'CD' + AB'C'D
gate103:A
gate103:B
gate103:OUT
gate104:A
gate104:B
gate104:OUT
gate105:A
gate105:B
gate105:OUT
gate106:A
gate106:B
gate106:OUT
gate107:A
gate107:B
gate107:OUT
gate108:A
gate108:B
gate108:OUT
gate109:A
gate109:B
gate109:OUT
gate110:A
gate110:B
gate110:OUT
gate111:A
gate111:B
gate111:OUT
AB' + B'C' + A'B(C + D) + A'CD'
gate112:A
gate112:B
gate112:OUT
pwr17:GND
led8:A
led8:C
gate113:A
gate113:B
gate113:OUT
gate114:A
gate114:B
gate114:OUT
pwr18:GND
led9:A
led9:C
A'B(C+D) + B'(C'D' + CD)'
gate115:A
gate115:B
gate115:OUT
gate116:A
gate116:B
gate116:OUT
A'C + D(A^B) + B'C'D'
pwr19:GND
led10:A
led10:C
gate118:A
gate118:B
gate118:OUT
gate119:A
gate119:B
gate119:OUT
gate120:A
gate120:B
gate120:OUT
gate117:A
gate117:B
gate117:OUT
gate121:A
gate121:B
gate121:OUT
SR
flipflop4:D
flipflop4:CLK
flipflop4:S
flipflop4:R
flipflop4:Q
flipflop4:NOTQ
gate2:A
gate2:B
gate2:OUT
SR
flipflop7:D
flipflop7:CLK
flipflop7:S
flipflop7:R
flipflop7:Q
flipflop7:NOTQ
gate3:A
gate3:B
gate3:OUT
SR
flipflop8:D
flipflop8:CLK
flipflop8:S
flipflop8:R
flipflop8:Q
flipflop8:NOTQ
gate4:A
gate4:B
gate4:OUT
SR
flipflop9:D
flipflop9:CLK
flipflop9:S
flipflop9:R
flipflop9:Q
flipflop9:NOTQ
gate5:A
gate5:B
gate5:OUT
gate6:A
gate6:B
gate6:OUT
gate17:A
gate17:B
gate17:OUT
gate18:A
gate18:B
gate18:OUT
gate19:A
gate19:B
gate19:OUT
led11:A
led11:C
pwr4:GND
bargraph2:A1
bargraph2:A2
bargraph2:A3
bargraph2:A4
bargraph2:A5
bargraph2:A6
bargraph2:A7
bargraph2:A8
bargraph2:A9
bargraph2:A10
bargraph2:C1
bargraph2:C2
bargraph2:C3
bargraph2:C4
bargraph2:C5
bargraph2:C6
bargraph2:C7
bargraph2:C8
bargraph2:C9
bargraph2:C10
pwr5:GND
mux2:A
mux2:B
mux2:SEL
mux2:OUT
mux3:A
mux3:B
mux3:SEL
mux3:OUT
mux4:A
mux4:B
mux4:SEL
mux4:OUT
mux7:A
mux7:B
mux7:SEL
mux7:OUT
Check if counter == 12...if so send reset signal
not1:IN
not1:OUT
gnd1:GND
not2:IN
not2:OUT
and1:A
and1:B
and1:OUT
xor1:A
xor1:B
xor1:OUT
xor2:A
xor2:B
xor2:OUT
and2:A
and2:B
and2:OUT
xor3:A
xor3:B
xor3:OUT
sw1:1
sw1:2
sw1:3
pwr1:GND
not3:IN
not3:OUT
not4:IN
not4:OUT
not5:IN
not5:OUT
not6:IN
not6:OUT
not7:IN
not7:OUT
not8:IN
not8:OUT
not9:IN
not9:OUT
vcc1:VCC