// This file is not interesting - check "blink.chip.v" for the actual implementation,
// and blink.chip.json for the pin definition.

void setup() {
  // put your setup code here, to run once:

}

void loop() {
  // put your main code here, to run repeatedly:

}


verilog-blink.ino

diagram.json

/*
 * Verilog chip on Wokwi - Proof of Concept. 
 *
 * The name of the toplevel module must be `wokwi`, 
 * and all the inputs/outputs must be defined in "game-of-life-cell.chip.json" in the "pins" section.
 * Only 1-bit inputs/outputs are supported, but you can combine several inputs together
 * into a single internal wire.
 */

`default_nettype none

module wokwi(
    input CLK, 
    input RST, 
    input FALIVE, 
    input N0,
    input N1,
    input N2,
    input N3,
    input N4,
    input N5,
    input N6,
    input N7,
    output OUT,
    );

    game_of_life_cell cell1(
        .clk (CLK),
        .rst (RST),
        .revive (FALIVE),
        .enable (1),
        .neighbors ({N7, N6, N5, N4, N3, N2, N1, N0}),
        .alive (OUT)
    );
    
endmodule

module game_of_life_cell(
    input wire clk,
    input wire rst,
    input wire revive,
    input wire enable,
    input wire [7:0] neighbors,
    output reg alive
);
  wire [2:0]popcnt = 
    {2'b00, neighbors[0]} +
    {2'b00, neighbors[1]} +
    {2'b00, neighbors[2]} +
    {2'b00, neighbors[3]} +
    {2'b00, neighbors[4]} +
    {2'b00, neighbors[5]} +
    {2'b00, neighbors[6]} +
    {2'b00, neighbors[7]};
  
  wire spring_to_life = (popcnt == 3);
  wire stay_alive = (popcnt == 2);

  always @(posedge clk) begin
    if (rst) alive <= 0;
    else if (revive) alive <= 1;
    else if (enable) alive <= spring_to_life || (alive && stay_alive);
  end
endmodule