#include "wokwi-api.h" #include #include #include // PROGRAMS: /* NOTE: this following program is the 'blink' program */ // int program[] = {1286, 0, 1030, 2560}; /* NOTE: this following program is the 'pattern' program */ // int program[] = {1510, 1478, 1446, 1414, 1382, 1350, 1318, 1286, 0, 1030, 1062, 1094, 1126, 1158, 1190, 1222, 1254, 2560}; /* NOTE: this following program is for incresing value of GPIO */ // int program[] = {678, 2560}; // INCF GPIO, 1 /* NOTE: this following program is smily face in dot-matrix */ int program[] = { 1318, 1062, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1318, 1062, 1318, 1062, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1318, 1062, 1318, 1062, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1350, 1286, 1030, 1094, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1094, 1286, 1030, 1318, 1062, 1318, 1062, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1094, 1286, 1030, 1286, 1030, 1286, 1030, 1350, 1286, 1030, 1286, 1030, 1286, 1030, 1286, 1030, 1094, 1286, 1030, 1286, 1030, 1318, 1062, 3 }; // opcodes as ENUM typedef enum OPCODES { NOP_OP, BCF_OP, BSF_OP, GOTO_OP, MOVLW_OP, MOVWF_OP, CLRF_OP, CLRW_OP, DECF_OP, DECFSZ_OP, INCF_OP, INCFSZ_OP, BTFSS_OP, BTFSC_OP, SLEEP_OP, ADDWF_OP, ANDWF_OP, COMF_OP, IORWF_OP, MOVF_OP, RLF_OP, RRF_OP, SUBWF_OP, SWAPF_OP, XORWF_OP, ANDLW_OP, CALL_OP, CLRWDT_OP, IORLW_OP, OPTION_OP, RETLW_OP, TRIS_OP, XORLW_OP, } OPCODES; typedef struct FETCH { int pc; // Program Counter int data; // Binary data } FETCH; typedef enum EXEC_TYPE { SIX_ONE_FIVE, FOUR_THREE_FIVE, FOUR_EIGHT, THREE_NINE, SEVEN_FIVE, FULL, } exec_t; typedef enum mem_t { TO_RAM, TO_REG, } mem_t; /* Decode Instruction */ typedef struct DECODE { OPCODES opcode; // OpCode int operand; // everything except OpCode int bits; // Part a Operand (bits) int addr; // Part b Operand (addr) char *info; // instruction info exec_t type; // Instruction type (multi operand or mono) } DECODE; typedef struct EXEC { int upc; // Updated PC (Program Counter) int sleep; } EXEC; typedef struct MEM_OUT { mem_t type; int addr; int value; int valid; } MEM_OUT; #define ROMSIZ 256 #define RAMSIZ 16 #define REGSIZ 10 #define MAX_STACK 2 // Max Stack (CALL & RETLW) static uint8_t _stack[MAX_STACK]; static int INPUT_EN = 0; // Memory // unsigned short rom[ROMSIZ]; // uint16_t // unsigned char ram[RAMSIZ]; // uint8_t // unsigned char reg[REGSIZ]; // uint8_t short int ROM[ROMSIZ]; uint8_t RAM[RAMSIZ]; uint8_t REGISTERS[REGSIZ]; typedef enum SFR { INDF_REGISTER, TMR0_REGISTER, PCL_REGISTER, STATUS_REGISTER, FSR_REGISTER, OSCCAL_REGISTER, GPIO_REGISTER, CMCON0_REGISTER, TRISGPIO_REGISTER, OPTION_REGISTER } SFR; static int WReg = 0; static int CARRY_VAL = 0; /* STACK */ void push_stack(uint8_t value){ for(int i = MAX_STACK - 1; i > 0; --i){ _stack[i] = _stack[i - 1]; } _stack[0] = value; } uint8_t pop_stack(void){ uint8_t popped = _stack[0]; for(int i = MAX_STACK - 1; i > 0; --i){ _stack[i - 1] = _stack[i]; } return popped; } /* Rotate And Carry */ void set_carry(int val){ CARRY_VAL = val; } int get_carry(){ return CARRY_VAL; } int rotate_left_carry(uint8_t value){ set_carry((value & 0x80) >> 7); return (value << 1) | (get_carry() & 0x01); } int rotate_right_carry(uint8_t value) { set_carry(value & 1); return (value >> 1) | (get_carry() << 7); } /* SFR */ void set_sfr_bit(SFR sfr, int bitnum){ int regv = REGISTERS[sfr]; bitnum %= 8; regv |= (1 << bitnum); REGISTERS[sfr] = regv; } /* Set given bit of SRF to 0 */ void clear_sfr_bit(SFR sfr, int bitnum){ int regv = REGISTERS[sfr]; bitnum %= 8; regv &= ~(1 << bitnum); REGISTERS[sfr] = regv; } /* set srf value */ void set_sfr(SFR sfr, int literal){ if(literal > 255){ literal = 0; } REGISTERS[sfr] = literal; } /* get srf value */ int get_sfr(SFR sfr){ return REGISTERS[sfr]; } // MEM_OUT get_mem(REG *reg, RAM *ram, int addr){ MEM_OUT get_mem(int addr){ MEM_OUT mem; mem.valid = 1; if(addr <= (REGSIZ - 1)){ mem.type = TO_REG; mem.addr = addr; mem.value = REGISTERS[mem.addr]; } else if (addr >= REGSIZ && addr <= (RAMSIZ - 1)){ mem.type = TO_RAM; mem.addr = addr - REGSIZ; mem.value = RAM[mem.addr]; } else { mem.valid = 0; } return mem; } int set_mem(MEM_OUT mem, int val){ if(mem.valid == 0){ return 1; } if(mem.type == TO_REG){ REGISTERS[mem.addr] = val; return 0; } else if (mem.type == TO_RAM){ REGISTERS[mem.addr] = val; return 0; } return 1; } void set_w_reg(int val){ WReg = val; } int get_w_reg(){ return WReg; } typedef struct { int frequency; // CPU frequency timer_config_t config; // CPU timer config timer_t timer_id; // CPU timer id } chip_state_t; static int pc = 0; // Program Counter // GPIO thread timer & id timer_config_t gpio_conf; timer_t gpio_timer; // Output pins for GPIO 6 pin_t out_pins[8]; void cpu_cycle(void *user_data); // CPU's life cycle void gpio_handler(void *user_data); // gpio handler cycle /* Extract Decimal from binary (start and end are included)*/ int edfb(int decimal, int start, int end) { start--; end--; // Create a mask to extract the desired bits int mask = (1 << (end - start + 1)) - 1; // Shift the mask to the correct position mask <<= start; // Extract the desired bits int ebits = (decimal & mask) >> start; return ebits; } void chip_init() { chip_state_t *chip = malloc(sizeof(chip_state_t)); // Initialize chip->frequency = 100; // Convert user input frequency into valid frequency for CPU if(chip->frequency == 0) chip->frequency = 500000; else if (chip->frequency > 1000000) chip->frequency = 1; else chip->frequency = 1000000 / chip->frequency; // Update the ROM by given program for(int i = 0; i < sizeof(program) / sizeof(program[0]); ++i) ROM[i] = program[i]; // Setup pins char *pins[] = {"GPIO-8", "GPIO-7", "GPIO-6", "GPIO-5", "GPIO-4", "GPIO-3", "GPIO-2", "GPIO-1"}; for(int i = 0; i < 8; i++){ out_pins[i] = pin_init(pins[i], OUTPUT); } // Start CPU cycle chip->config.callback = cpu_cycle; chip->timer_id = timer_init(&chip->config); timer_start(chip->timer_id, chip->frequency, true); // Start GPIO cycle gpio_conf.callback = gpio_handler; gpio_timer = timer_init(&gpio_conf); timer_start(gpio_timer, chip->frequency / 2, true); } // Update GPIO(1..8) that are attached to the 'reg[6]' void gpio_handler(void *user_data){ int num, i; i = 0; num = REGISTERS[6]; // printf("GPIO 6: %d\n", num); int mask = 1 << 7; // 10000000 for (int i = 0; i < 8; i++) { if (num & mask) { pin_write(out_pins[i], HIGH); } else { pin_write(out_pins[i], LOW); } mask >>= 1; // remove one '0' at a time from right } } DECODE decode_inst(int inst){ DECODE dcd; dcd.bits = dcd.addr = 0; // NOP if(inst == 0b000000000000){ dcd.opcode = NOP_OP; dcd.type = FULL; dcd.info = "NOP"; // CLRW } else if(inst == 0b000001000000){ dcd.opcode = CLRW_OP; dcd.type = FULL; dcd.info = "CLRW"; // SLEEP } else if(inst == 0b000000000011){ dcd.opcode = SLEEP_OP; dcd.type = FULL; dcd.info = "SLEEP"; // BSF } else if(edfb(inst, 9, 12) == 0b0101){ dcd.opcode = BSF_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_THREE_FIVE; dcd.info = "BSF"; dcd.bits = edfb(inst, 6, 8); dcd.addr = edfb(inst, 1, 5); // BCF } else if(edfb(inst, 9, 12) == 0b0100){ dcd.opcode = BCF_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_THREE_FIVE; dcd.info = "BCF"; dcd.bits = edfb(inst, 6, 8); dcd.addr = edfb(inst, 1, 5); // MOVLW } else if(edfb(inst, 9, 12) == 0b1100){ dcd.opcode = MOVLW_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_EIGHT; dcd.info = "MOVLW"; dcd.bits = edfb(inst, 1, 8); // MOVWF } else if(edfb(inst, 6, 12) == 0b0000001){ dcd.opcode = MOVWF_OP; dcd.operand = edfb(inst, 1, 5); dcd.type = SEVEN_FIVE; dcd.info = "MOVWF"; dcd.addr = edfb(inst, 1, 5); // CLRF } else if(edfb(inst, 6, 12) == 0b0000011){ dcd.opcode = CLRF_OP; dcd.operand = edfb(inst, 1, 5); dcd.type = SEVEN_FIVE; dcd.info = "CLRF"; dcd.addr = edfb(inst, 1, 5); // DECF } else if(edfb(inst, 7, 12) == 0b000011){ dcd.opcode = DECF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "DECF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // DECFSZ } else if(edfb(inst, 7, 12) == 0b001011){ dcd.opcode = DECFSZ_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "DECFSZ"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // INCF } else if(edfb(inst, 7, 12) == 0b001010){ dcd.opcode = INCF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "INCF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // INCFSZ } else if(edfb(inst, 7, 12) == 0b001111){ dcd.opcode = INCFSZ_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "INCFSZ"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // BTFSS } else if(edfb(inst, 9, 12) == 0b0110){ dcd.opcode = BTFSS_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_THREE_FIVE; dcd.info = "BTFSS"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 8); // BTFSC } else if(edfb(inst, 9, 12) == 0b0111){ dcd.opcode = BTFSC_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_THREE_FIVE; dcd.info = "BTFSC"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 8); // GOTO } else if(edfb(inst, 10, 12) == 0b101){ dcd.opcode = GOTO_OP; dcd.operand = edfb(inst, 1, 9); dcd.type = THREE_NINE; dcd.info = "GOTO"; dcd.addr = edfb(inst, 1, 9); // ADDWF } else if(edfb(inst, 7, 12) == 0b000111){ dcd.opcode = ADDWF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "ADDWF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // ANDWF } else if(edfb(inst, 7, 12) == 0b000101){ dcd.opcode = ANDWF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "ANDWF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // COMF } else if(edfb(inst, 7, 12) == 0b001001){ dcd.opcode = COMF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "COMF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // IORWF } else if(edfb(inst, 7, 12) == 0b000100){ dcd.opcode = IORWF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "IORWF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // MOVF } else if(edfb(inst, 7, 12) == 0b001000){ dcd.opcode = MOVF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "MOVF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // RLF } else if(edfb(inst, 7, 12) == 0b001101){ dcd.opcode = RLF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "RLF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // RRF } else if(edfb(inst, 7, 12) == 0b001100){ dcd.opcode = RRF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "RRF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // SUBWF } else if(edfb(inst, 7, 12) == 0b000010){ dcd.opcode = SUBWF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "SUBWF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // SWAPF } else if(edfb(inst, 7, 12) == 0b001110){ dcd.opcode = SWAPF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "SWAPF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // XORWF } else if(edfb(inst, 7, 12) == 0b000110){ dcd.opcode = XORWF_OP; dcd.operand = edfb(inst, 1, 6); dcd.type = SIX_ONE_FIVE; dcd.info = "XORWF"; dcd.addr = edfb(inst, 1, 5); dcd.bits = edfb(inst, 6, 6); // ANDLW } else if(edfb(inst, 9, 12) == 0b1110){ dcd.opcode = ANDLW_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_EIGHT; dcd.info = "ANDLW"; dcd.bits = edfb(inst, 1, 8); // CALL } else if(edfb(inst, 9, 12) == 0b1001){ dcd.opcode = CALL_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_EIGHT; dcd.info = "CALL"; dcd.addr = edfb(inst, 1, 8); // CLRWDT } else if(edfb(inst, 1, 12) == 0b000000000100){ dcd.opcode = CLRWDT_OP; dcd.operand = edfb(inst, 1, 12); dcd.type = FULL; dcd.info = "CLRWDT"; // IORLW } else if(edfb(inst, 9, 12) == 0b1101){ dcd.opcode = IORLW_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_EIGHT; dcd.info = "IORLW"; dcd.bits = edfb(inst, 1, 8); // OPTION } else if(edfb(inst, 1, 12) == 0b000000000010){ dcd.opcode = OPTION_OP; dcd.operand = edfb(inst, 1, 12); dcd.type = FULL; dcd.info = "OPTION"; // RETLW } else if(edfb(inst, 9, 12) == 0b1000){ dcd.opcode = RETLW_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_EIGHT; dcd.info = "RETLW"; dcd.bits = edfb(inst, 1, 8); // XORLW } else if(edfb(inst, 9, 12) == 0b1111){ dcd.opcode = XORLW_OP; dcd.operand = edfb(inst, 1, 8); dcd.type = FOUR_EIGHT; dcd.info = "XORLW"; dcd.bits = edfb(inst, 1, 8); // TRIS } else if(edfb(inst, 1, 12) == 0b000000000110 || edfb(inst, 1, 12) == 0b000000000111){ dcd.opcode = TRIS_OP; dcd.operand = edfb(inst, 1, 3); dcd.type = FULL; dcd.info = "TRIS"; dcd.addr = edfb(inst, 1, 3); // Undefined } else dcd.opcode = NOP_OP; return dcd; } // put value into register 'W' if 'dcd.bits == 0' otherwise put if 'f' register void update_by_dist(MEM_OUT mem, DECODE dcd){ if(dcd.bits == 1){ set_mem(mem, mem.value); } else { set_w_reg(mem.value); } } EXEC soft_execute(DECODE dcd){ EXEC exec; exec.sleep = 0; exec.upc = pc; switch(dcd.opcode) { case GOTO_OP: exec.upc = dcd.operand; break; case SLEEP_OP: exec.sleep = 1; break; case CALL_OP: push_stack(pc + 1); // (PC + 1) to Stack-1 // (PC) exec.upc = dcd.addr; break; case RETLW_OP: exec.upc = pop_stack(); // Stack-1 to PC set_w_reg(dcd.bits); // Load Register W break; default: break; } return exec; } /* Execute & Update Memory etc... */ int execute(DECODE dcd){ MEM_OUT m; int bypass = 0; switch(dcd.opcode) { // BSF case BSF_OP: m = get_mem(dcd.addr); set_mem(m, m.value | (1 << dcd.bits)); break; // BCF case BCF_OP: m = get_mem(dcd.addr); set_mem(m, m.value & ~(1 << dcd.bits)); break; // MOVLW case MOVLW_OP: set_w_reg(dcd.bits); break; // MOVWF case MOVWF_OP: m = get_mem(dcd.addr); set_mem(m, get_w_reg()); break; // CLRF case CLRF_OP: m = get_mem(dcd.addr); set_mem(m, 0); break; // CLRW case CLRW_OP: set_w_reg(0); break; // DECF case DECF_OP: m = get_mem(dcd.addr); if(m.value != 0){ m.value--; clear_sfr_bit(STATUS_REGISTER, 2); } else { set_sfr_bit(STATUS_REGISTER, 2); } update_by_dist(m, dcd); break; // DECFSZ case DECFSZ_OP: m = get_mem(dcd.addr); if(m.value != 0){ m.value--; clear_sfr_bit(STATUS_REGISTER, 2); } else { set_sfr_bit(STATUS_REGISTER, 2); } update_by_dist(m, dcd); if(m.value == 0){ bypass = 1; } break; // INCF case INCF_OP: m = get_mem(dcd.addr); if(m.value != 255){ m.value++; clear_sfr_bit(STATUS_REGISTER, 2); } else { m.value = 0; set_sfr_bit(STATUS_REGISTER, 2); } update_by_dist(m, dcd); break; // INCFSZ case INCFSZ_OP: m = get_mem(dcd.addr); if(m.value != 255){ m.value++; clear_sfr_bit(STATUS_REGISTER, 2); } else { m.value = 0; set_sfr_bit(STATUS_REGISTER, 2); } update_by_dist(m, dcd); if(m.value == 0){ bypass = 1; } break; // BTFSS case BTFSS_OP: m = get_mem(dcd.addr); if(edfb(m.value, dcd.bits + 1, dcd.bits + 1) == 1){ bypass = 1; } break; // BTFSC case BTFSC_OP: m = get_mem(dcd.addr); if(edfb(m.value, dcd.bits + 1, dcd.bits + 1) == 0){ bypass = 1; } break; // ADDWF case ADDWF_OP: m = get_mem(dcd.addr); m.value = m.value + get_w_reg(); if(m.value > 255){ m.value = 0; clear_sfr_bit(STATUS_REGISTER, 1); set_sfr_bit(STATUS_REGISTER, 2); } else { set_sfr_bit(STATUS_REGISTER, 1); clear_sfr_bit(STATUS_REGISTER, 2); } update_by_dist(m, dcd); break; // ANDWF case ANDWF_OP: m = get_mem(dcd.addr); m.value &= get_w_reg(); update_by_dist(m, dcd); break; // COMF case COMF_OP: m = get_mem(dcd.addr); m.value = ~m.value; update_by_dist(m, dcd); break; // IORWF case IORWF_OP: m = get_mem(dcd.addr); m.value |= get_w_reg(); update_by_dist(m, dcd); break; // MOVF case MOVF_OP: m = get_mem(dcd.addr); update_by_dist(m, dcd); break; // RLF case RLF_OP: m = get_mem(dcd.addr); m.value = rotate_left_carry(m.value); update_by_dist(m, dcd); break; // RRF case RRF_OP: m = get_mem(dcd.addr); m.value = rotate_right_carry(m.value); update_by_dist(m, dcd); break; // SUBWF (W - f) case SUBWF_OP: m = get_mem(dcd.addr); m.value = get_w_reg() - m.value; if(m.value < 0){ m.value = 0; clear_sfr_bit(STATUS_REGISTER, 1); set_sfr_bit(STATUS_REGISTER, 2); } else { set_sfr_bit(STATUS_REGISTER, 1); clear_sfr_bit(STATUS_REGISTER, 2); } update_by_dist(m, dcd); break; // SWAPF case SWAPF_OP: m = get_mem(dcd.addr); m.value = (m.value >> 4) | (m.value << 4); update_by_dist(m, dcd); break; // XORWF case XORWF_OP: m = get_mem(dcd.addr); m.value = m.value ^ get_w_reg(); update_by_dist(m, dcd); break; // XORWF case ANDLW_OP: set_w_reg(get_w_reg() & dcd.bits); break; // CLRWDT case CLRWDT_OP: set_sfr_bit(STATUS_REGISTER, 3); set_sfr_bit(STATUS_REGISTER, 4); set_sfr(TMR0_REGISTER, 0); // clear TIMER break; // IORLW case IORLW_OP: set_w_reg(get_w_reg() | dcd.bits); break; // OPTION case OPTION_OP: set_sfr(OPTION_REGISTER, get_w_reg()); break; // CLRWDT case TRIS_OP: set_sfr(TRISGPIO_REGISTER, dcd.addr); if(dcd.addr == 6){ INPUT_EN = 1; } else { INPUT_EN = 0; } break; // XORLW case XORLW_OP: set_w_reg(get_w_reg() ^ dcd.bits); break; default: break; } return bypass; } // Main cycle (CPU) void cpu_cycle(void *user_data){ FETCH fetch; EXEC exec; DECODE dcd; int bypass = 0; fetch = (FETCH){pc, ROM[pc]}; // fetch one instruction at a time dcd = decode_inst(fetch.data); // decode the given instruction exec = soft_execute(dcd); // set execute data for the instruction // show current executing OpCode & state of register number 6 printf("Execute: (%-5s), REG 6: 0x%x | W: 0x%x\n", dcd.info, REGISTERS[6], get_w_reg()); if(exec.sleep == 0){ // Update the PC & check for goto if(exec.upc == pc){ pc++; } else{ pc = exec.upc; } } // Update memory bypass = execute(dcd); if(bypass){ pc = pc + 1; } }