# Joseph's 8 Bit CPU (or at least aspiring to be)

## Wires

green: general data
white: clock
(no longer in use: causes hold violation)~~grey: clock w/ some sort of logic~~ 
blue: bus
orange: user-input

## Components

The ALU is the vertical line towards the bottom. It can currently only add.

The bus is the sequence of OR gates. I couldn't find another way to represent a line that could be joined like a bus would, so I figured representing it as an OR gate with ground would make the most sense although it is certainly not the most efficient.

Towards the top, a shift-register can be found that allows the user to interact with the bus.

## Input

IN1: serial Input
IN2: output shift-register to bus?
IN3: DIR for register A (in by default)
IN4: DIR for register B (in by default)
IN5: ALU output
IN6: load register A
IN7: load register B
IN8: Add/Sub