#define GPIOA_BASEADDR        0x50000000U 
#define RCC_BASEADDR          0x40021000U
#define GPIOA_PCLK_EN()       ((RCC->IOPENR) |= (1 << 0))
#define ADC_PCLK_EN()           ((RCC->APBENR2) |= (1 << 20))
#define ADC_BASEADDR          0x40012400U

typedef struct
{
  volatile   uint32_t    ISR;
  volatile   uint32_t    IER;
  volatile   uint32_t    CR;
  volatile   uint32_t    CFGR1;
  volatile   uint32_t    CFGR2;
  volatile   uint32_t    SMPR;
  volatile   uint32_t    Reserved[2];
  volatile   uint32_t    AWD1TR;
  volatile   uint32_t    AWD2TR;
  volatile   uint32_t    CHSELR1;
  volatile   uint32_t    AWD3TR;
  volatile   uint32_t    Reserved1[4];
  volatile   uint32_t    DR;
  volatile   uint32_t    Reserved2[17];
  volatile   uint32_t    AWD2CR;
  volatile   uint32_t    WD3CR;
  volatile   uint32_t    Reserved3[3];
  volatile   uint32_t    CALFACT;
  volatile   uint32_t    Reserved4[94];
  volatile   uint32_t    CCR;
}ADC_RegConfig_t;
typedef struct 
{
    volatile uint32_t MODER;
    volatile uint32_t OTYPER;
    volatile uint32_t OSPEEDR;
    volatile uint32_t PUPDR;
    volatile uint32_t IDR;
    volatile uint32_t ODR;
    volatile uint32_t BSRR;
    volatile uint32_t LCKR;
    volatile uint32_t AFR[0];
} GPIO_RegConfig_t;

typedef struct 
{
    volatile uint32_t CR;
    volatile uint32_t ICSCR;
    volatile uint32_t CFGR;
    volatile uint32_t Reserved0[2];
    volatile uint32_t CRRCR;
    volatile uint32_t CIER;
    volatile uint32_t CIFR;
    volatile uint32_t CICR;
    volatile uint32_t IOPRSTR;
    volatile uint32_t AHBRSTR;
    volatile uint32_t APBRSTR1;
    volatile uint32_t APBRSTR2;
    volatile uint32_t IOPENR;
    volatile uint32_t AHBENR;
    volatile uint32_t APBENR1;
    volatile uint32_t APBENR2;
    volatile uint32_t IOPSMENR;
    volatile uint32_t AHBSMENR;
    volatile uint32_t APBSMENR1;
    volatile uint32_t APBSMENR2;
    volatile uint32_t CCIPR;
    volatile uint32_t CCIPR2;
    volatile uint32_t CSR1;
    volatile uint32_t CSR2;
} RCC_RegConfig_t;

#define RCC           ((RCC_RegConfig_t*)RCC_BASEADDR)
#define GPIOA         ((GPIO_RegConfig_t*)GPIOA_BASEADDR)
#define ADC            ((ADC_RegConfig_t*)ADC_BASEADDR)


void ADC_Init() {
    ADC->CR |= (1 << 0); // Enable ADC
    while (!(ADC->CR & (1 << 0))); // Wait for ADC to be ready

    // Configure ADC (resolution, alignment, etc.) here
    ADC->CFGR1=0;
    
    // Select channel
    ADC->CHSELR1 |= (1 << 0); // Select channel 0
}

uint16_t Read_ADC() {
    ADC->CR |= (1 << 2); // Start conversion
    while (!(ADC->ISR & (1 << 2))); // Wait for conversion complete
    return ADC->DR; // Read data register
}

void setup() {
    Serial.begin(115200);
    Serial.println("Hello, STM32!");
    GPIOA_PCLK_EN();
    ADC_PCLK_EN();
    
    // Configure PA0 for ADC
    GPIOA->MODER &= ~(3 << 0); // Clear PA0 bits
    GPIOA->MODER |= (3 << 0);  // PA0 as analog mode
    
    ADC_Init();
    
    while (1) {
        uint16_t dataValue = Read_ADC();
        const float BETA = 3950; // should match the Beta Coefficient of the thermistor
        float celsius = 1 / (log(1 / (4096. / dataValue - 1)) / BETA + 1.0 / 298.15) - 273.15;
        Serial.println(celsius);
        mydelay(); // Call delay if necessary
    }
}
void loop() {}
void mydelay()
{
uint32_t i=0;
for(i=0;i<10000;i++);
}