# Tiny Tapeout 9 Template Project

TinyTapeout is an educational project that makes it easier and cheaper
than ever to get your digital designs manufactured on a real chip.

Wokwi provides an easy way to create digital designs for Tiny Tapeout. 
You create a design out of individual logic gates, and simulate them 
with Wokwi to observe the result.

When your design is ready, you can submit it for manufacturing on a 
physical chip with Tiny Tapeout.

To learn more, follow the tutorial at https://tinytapeout.com/digital_design/

Note: when creating your own project, please replace this text with information
about your projects: what it does and how to use it.


README.md

diagram.json

sm.chip.json

module wokwi (
    input clk,
    input rst,         // Added reset input for initialization
    input [7:0] in,    // Input switches
    output [7:0] out   // Output for current state
);

    reg [7:0] state;   // Current state register
    wire next_start, next_s1, next_s2, next_s3, next_s4, next_s5, next_s6, next_s7;

    // State Encoding
    wire start = state[0];
    wire s1 = state[1];
    wire s2 = state[2];
    wire s3 = state[3];
    wire s4 = state[4];
    wire s5 = state[5];
    wire s6 = state[6];
    wire s7 = state[7];

    wire [7:0] in = {IN7,IN6,IN5,IN4,IN3,IN2,IN1.IN0};

    // Flip-Flops to hold state (using custom FDRE below with reset support)
    FDRE Q0_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_start), .Q(state[0]));
    FDRE Q1_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s1), .Q(state[1]));
    FDRE Q2_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s2), .Q(state[2]));
    FDRE Q3_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s3), .Q(state[3]));
    FDRE Q4_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s4), .Q(state[4]));
    FDRE Q5_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s5), .Q(state[5]));
    FDRE Q6_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s6), .Q(state[6]));
    FDRE Q7_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s7), .Q(state[7]));

    // State Transition Logic
    assign next_start = ~|state[7:1] | (IN0 | IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & start
                        | (IN0 | IN1 | IN2 | IN3 | IN4 | IN5 | IN7) & s1
                        | (IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & s2
                        | (IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & s3
                        | (IN0 | IN1 | IN2 | IN3 | IN4 | IN5 | IN7) & s4
                        | (IN0 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & s5
                        | (IN0 | IN1 | IN2 | IN4 | IN5 | IN6 | IN7) & s6
                        | (IN0 | IN1 | IN2 | IN3 | IN4 | IN6 | IN7) & s7;
    assign next_s1 = start & (in == 8'b01000000) | s1 & (in == 8'b01000000);       
    assign next_s2 = s1 & (in == 8'b01000001) | s2 & (in == 8'b01000001);       
    assign next_s3 = s2 & (in == 8'b01000000) | s3 & (in == 8'b01000000);  
    assign next_s4 = s3 & (in == 8'b00000000) | s4 & (in == 8'b00000000);       
    assign next_s5 = s4 & (in == 8'b00000010) | s5 & (in == 8'b00000010); 
    assign next_s6 = s5 & (in == 8'b00001010) | s6 & (in == 8'b00001010); 
    assign next_s7 = s6 & (in == 8'b00101010) | s7;                     

    // Output state
    assign out = state;
endmodule

// Custom FDRE Module with Reset Support
module FDRE (
    input C,           // Clock
    input R,           // Reset (active high)
    input CE,          // Clock Enable
    input D,           // Data input
    output reg Q       // Data output (flip-flop state)
);

    always @(posedge C or posedge R) begin
        if (R) 
            Q <= 1'b0; // Asynchronous reset to 0
        else if (CE) 
            Q <= D;    // Clock enable controls D input
    end
endmodule


sm.chip.v

statemachine

statemachine.chip.json

// Wokwi Custom Chip - For docs and examples see:
// https://docs.wokwi.com/chips-api/getting-started
//
// SPDX-License-Identifier: MIT
// Copyright 2023 Chad Baker

// Input / output names must match the pins defined in the chip's JSON file:
module wokwi (
  input wire IN,
  output wire OUT
  );

  // put your logic here, e.g.:
  assign OUT = ~IN;

endmodule

statemachine.chip.v

scsm

scsm.chip.json

// Wokwi Custom Chip - For docs and examples see:
// https://docs.wokwi.com/chips-api/getting-started
//
// SPDX-License-Identifier: MIT
// Copyright 2023 Chad Baker

// Input / output names must match the pins defined in the chip's JSON file:
module wokwi (
  input clk,
    input rst,         // Added reset input for initialization
    input [7:0] in,    // Input switches
    output [7:0] out   // Output for current state
);

    reg [7:0] state;   // Current state register
    wire next_start, next_s1, next_s2, next_s3, next_s4, next_s5, next_s6, next_s7;

    // State Encoding
    wire start = state[0];
    wire s1 = state[1];
    wire s2 = state[2];
    wire s3 = state[3];
    wire s4 = state[4];
    wire s5 = state[5];
    wire s6 = state[6];
    wire s7 = state[7];

    wire [7:0] in = {IN7,IN6,IN5,IN4,IN3,IN2,IN1.IN0};

    // Flip-Flops to hold state (using custom FDRE below with reset support)
    FDRE Q0_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_start), .Q(state[0]));
    FDRE Q1_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s1), .Q(state[1]));
    FDRE Q2_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s2), .Q(state[2]));
    FDRE Q3_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s3), .Q(state[3]));
    FDRE Q4_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s4), .Q(state[4]));
    FDRE Q5_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s5), .Q(state[5]));
    FDRE Q6_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s6), .Q(state[6]));
    FDRE Q7_FF (.C(clk), .R(rst), .CE(1'b1), .D(next_s7), .Q(state[7]));

    // State Transition Logic
    assign next_start = ~|state[7:1] | (IN0 | IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & start
                        | (IN0 | IN1 | IN2 | IN3 | IN4 | IN5 | IN7) & s1
                        | (IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & s2
                        | (IN1 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & s3
                        | (IN0 | IN1 | IN2 | IN3 | IN4 | IN5 | IN7) & s4
                        | (IN0 | IN2 | IN3 | IN4 | IN5 | IN6 | IN7) & s5
                        | (IN0 | IN1 | IN2 | IN4 | IN5 | IN6 | IN7) & s6
                        | (IN0 | IN1 | IN2 | IN3 | IN4 | IN6 | IN7) & s7;
    assign next_s1 = start & (in == 8'b01000000) | s1 & (in == 8'b01000000);       
    assign next_s2 = s1 & (in == 8'b01000001) | s2 & (in == 8'b01000001);       
    assign next_s3 = s2 & (in == 8'b01000000) | s3 & (in == 8'b01000000);  
    assign next_s4 = s3 & (in == 8'b00000000) | s4 & (in == 8'b00000000);       
    assign next_s5 = s4 & (in == 8'b00000010) | s5 & (in == 8'b00000010); 
    assign next_s6 = s5 & (in == 8'b00001010) | s6 & (in == 8'b00001010); 
    assign next_s7 = s6 & (in == 8'b00101010) | s7;                     

    // Output state
    assign out = state;
endmodule

// Custom FDRE Module with Reset Support
module FDRE (
    input C,           // Clock
    input R,           // Reset (active high)
    input CE,          // Clock Enable
    input D,           // Data input
    output reg Q       // Data output (flip-flop state)
);

    always @(posedge C or posedge R) begin
        if (R) 
            Q <= 1'b0; // Asynchronous reset to 0
        else if (CE) 
            Q <= D;    // Clock enable controls D input
    end
endmodule