/** ****************************************************************************** * @file stm32l031xx.h * @author MCD Application Team * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for stm32l031xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * * Copyright (c) 2016 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file * in the root directory of this software component. * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32l031xx * @{ */ #ifndef __STM32L031xx_H #define __STM32L031xx_H #ifdef __cplusplus extern "C" { #endif /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ #define __CM0PLUS_REV 0U /*!< Core Revision r0p0 */ #define __MPU_PRESENT 0U /*!< STM32L0xx provides no MPU */ #define __VTOR_PRESENT 1U /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 2U /*!< STM32L0xx uses 2 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief stm32l031xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ typedef enum { /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ /****** STM32L-0 specific Interrupt Numbers *********************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ FLASH_IRQn = 3, /*!< FLASH Interrupt */ RCC_IRQn = 4, /*!< RCC Interrupt */ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ TIM2_IRQn = 15, /*!< TIM2 Interrupt */ TIM21_IRQn = 20, /*!< TIM21 Interrupt */ TIM22_IRQn = 22, /*!< TIM22 Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt */ SPI1_IRQn = 25, /*!< SPI1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ LPUART1_IRQn = 29, /*!< LPUART1 Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm0plus.h" #include "system_stm32l0xx.h" #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ uint32_t RESERVED3; /*!< Reserved, 0x24 */ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ } ADC_TypeDef; typedef struct { __IO uint32_t CCR; } ADC_Common_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; typedef struct { __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ } DMA_Request_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!