void setupTimer0() {
  noInterrupts();
  // Clear registers
  TCCR0A = 0;
  TCCR0B = 0;
  TCNT0 = 0;

  // 1 Hz (16000000/((124+1)*1024)) ≈ 125 Hz
  // For 1 Hz, we need OCR0A = 15624 but Timer0 is 8-bit
  // We'll need to adjust the prescaler or count more interrupts
  OCR0A = 124;  
  // CTC mode
  TCCR0A |= (1 << WGM01);
  // Prescaler 1024
  TCCR0B |= (1 << CS02) | (1 << CS00);
  // Output Compare Match A Interrupt Enable
  TIMSK0 |= (1 << OCIE0A);
  interrupts();
}

void setupTimer1() {
  noInterrupts();
  // Clear registers
  TCCR1A = 0;
  TCCR1B = 0;
  TCNT1 = 0;

  // 2 Hz = (16000000/((7812+1)*1024)) ≈ 2.00 Hz
  OCR1A = 7812;
  // CTC mode
  TCCR1B |= (1 << WGM12);
  // Prescaler 1024
  TCCR1B |= (1 << CS12) | (1 << CS10);
  // Output Compare Match A Interrupt Enable
  TIMSK1 |= (1 << OCIE1A);
  interrupts();
}

void setupTimer2() {
  noInterrupts();
  // Clear registers
  TCCR2A = 0;
  TCCR2B = 0;
  TCNT2 = 0;

  // 5 Hz = (16000000/((124+1)*256)) ≈ 500 Hz
  // Need to count multiple interrupts to achieve 5 Hz
  OCR2A = 124;
  // CTC mode
  TCCR2A |= (1 << WGM21);
  // Prescaler 256 (changed from 1024 for better accuracy)
  TCCR2B |= (1 << CS22) | (1 << CS21);
  // Output Compare Match A Interrupt Enable
  TIMSK2 |= (1 << OCIE2A);
  interrupts();
}

void setupTimer3() {
  noInterrupts();
  // Clear registers
  TCCR3A = 0;
  TCCR3B = 0;
  TCNT3 = 0;

  // 10 Hz = (16000000/((1562+1)*1024)) ≈ 10.00 Hz
  OCR3A = 1562;
  // CTC mode
  TCCR3B |= (1 << WGM32);
  // Prescaler 1024
  TCCR3B |= (1 << CS32) | (1 << CS30);
  // Output Compare Match A Interrupt Enable
  TIMSK3 |= (1 << OCIE3A);
  interrupts();
}

volatile uint8_t timer0_count = 0;
volatile uint8_t timer2_count = 0;

void setup() {
  DDRC = 0xFF;  // Set all PORTC pins as outputs
  setupTimer0();
  setupTimer1();
  setupTimer2();
  setupTimer3();
}

void loop() {
  // Empty - all work done in interrupts
}

ISR(TIMER0_COMPA_vect) {
  timer0_count++;
  if (timer0_count >= 125) {  // Divide by 125 to get 1 Hz
    PORTC ^= (1 << PC0) | (1 << PC1);
    timer0_count = 0;
  }
}

ISR(TIMER1_COMPA_vect) {
  PORTC ^= (1 << PC2) | (1 << PC3);
}

ISR(TIMER2_COMPA_vect) {
  timer2_count++;
  if (timer2_count >= 100) {  // Divide by 100 to get 5 Hz
    PORTC ^= (1 << PC4) | (1 << PC5);
    timer2_count = 0;
  }
}

ISR(TIMER3_COMPA_vect) {
  PORTC ^= (1 << PC6) | (1 << PC7);
}