# 74181 4-Bit ALU Demo

This is a recreation of the 74181 4 Bit ALU from the 1970s, in a setting
where we only use 8 input pins and provide inputs to the ALU circuit
from programmable 4-bit registers.

From an educational perspective, this circuit is interesting since
it features both programmable registers and an ALU. Hence,
"we are already halfway to understanding how a basic CPU works".

data bus:

IN0 = d0
IN1 = d1
IN2 = d2
IN3 = d3

control code:
IN4 = q0
IN5 = q1
IN6 = q2

## Usage

* Control codes (q0,q1,q2) = (0,?,?) are "inert", 
  while control codes of the form (1,?,?) are used to "program"
  the internal registers CTRL, A, B, S. This scheme allows us to
  even observe and experiment with ALU behavior using input from
  DIP switches if the circuit runs at MHz+ frequencies.

* Both for the simulator (where we should use clock-circuit input)
  and a real ASIC implementation based on this design, we can use
  this protocol:

  * Set all inputs to 0.
 
  * Activate "Reset"

  * Set d0 to M and d1 to the input-carry C.
    If we want to perform arithmetic operations with no incoming carry,
    we want to set both to zero.

  * Set (q0,q1,q2) to 100 and wait until we crossed at least
    one rising clock edge. This loads the values 
    of d0 and d1 into the 2-bit register (M, C).
    (If we want to select "logic mode", or set an input-carry,
    we can do this by setting d0 and d1 differently.)

  * Set (q0,q1,q2) to 000. This de-activates "M/C programming mode" and "freezes" these values.

  * Set (d0,d1,d2,d3) to the value that is to go into register A.
 
  * Set (q0,q1,q2) to 001.
 
  * Set (q0,q1,q2) to 101 and wait until we crossed at least one rising clock edge (as above).
 
  * Set q0 to 0, to de-activate "register-A programming mode".
    
    Register A now retains the value we programmed into it.

  * Set (d0,d1,d2,d3) to the value that is to go into register B.

  * Set (q0,q1,q2) to 010.

  * Set (q0,q1,q2) to 110 and wait as above.

  * Set q0 to 0, to de-activate "register-B programming mode".

  * Set (d0,d1,d2,d3) to the value that is to go into the S-register to select the ALU operation.
  
    See table at
    https://en.wikipedia.org/wiki/74181#Function_table_for_output_F:
    e.g. 1001 sets the ALU to "compute A+B+carry" if we also select
    "arithmetic mode".

  * Set (q0,q1,q2) to 011.

  * Set (q0,q1,q2) to 111 and wait as above.

  * Set q0 to 0.
   
     The output pins should show the result of the calculation.

# Reference

The circuit layout tries to closely follow the "reference schematics"
found e.g. on Wikipedia: https://en.wikipedia.org/wiki/74181
(Large version: https://upload.wikimedia.org/wikipedia/commons/c/c0/74181aluschematic.png)

Authoritative source for behavior: https://www.ti.com/lit/ds/symlink/sn54ls181.pdf

In the interest of keeping the circuit understandable,
optimization opportunities mostly were not exploited.

For example, the Bn signals are obtained by inverting the
/Bn signals where we might just as well have taken both
the Bn and the /Bn from the B-register flip flops. 

Towards the bottom-right of the reference schematics, there are 
some places where N-input ANDs (that we have to build from 2-input ANDs)
share sub-computations. In some such situations, we make use of the
obvious optimizations.

One such place is in the computation of C(n+4): the 5-input AND that
is the left input of the OR(-after-eliminating-negation) shares 4 
inputs with the 4-input AND used to compute P (actually /P in the
original circuit, but P here.)

# Original

This is a modified snapshot of: https://wokwi.com/projects/459636940965008385

# Status

This mostly seems to work, but there still seem to be some issues -
the C(n+4) logic seems to be not quite correct, for example.