# 2:1 mux with differential outputs

This is intended as general purpose mux but main application is to drive
a LVDS display using the FPD-Link protocol.

It also aims mitigate logic hazards, using XNOR gates to generate complementes
instead of a NOT gate which impose an unbalanced delay.

It is assumed that the clock (selection) signal will change at the same time as the input signals.

See https://en.wikipedia.org/wiki/Hazard_(logic)