# Tiny Tapeout 6-Bit Divider
This Wokwi circuit performs unsigned 6-bit division with a sequential restoring-divider architecture:
```text
numerator = quotient × denominator + remainder
```
The calculation reuses one 7-bit subtract/compare stage over six clock cycles.
## Inputs
| Input | Function |
| --- | --- |
| `CLK` | Advances all synchronous logic by one step |
| `RST_N` | Active-low reset |
| `IN0` | Data bit 0, least-significant bit |
| `IN1` | Data bit 1 |
| `IN2` | Data bit 2 |
| `IN3` | Data bit 3 |
| `IN4` | Data bit 4 |
| `IN5` | Data bit 5, most-significant bit |
| `IN6` | Input/result selector: `0` = numerator/quotient, `1` = denominator/remainder |
| `IN7` | Start input; a rising edge starts exactly one calculation |
`IN[5:0]` is an unsigned binary value from 0 to 63.
## How to use it
1. Pull `RST_N` low, then release it high.
2. Set `IN6 = 0`, enter the numerator on `IN[5:0]`, and give the circuit one clock edge so the numerator bank stores it.
3. Set `IN6 = 1` and enter the denominator on `IN[5:0]`.
4. Change `IN7` from `0` to `1` and give one clock edge. This captures the denominator and starts the divider.
5. Give six more clock edges. `DONE` then lights and the result is valid.
6. Keep `IN6 = 1` to read the remainder, or change it to `0` to read the quotient.
Before starting another calculation, set `IN7 = 0` and clock once so the start-edge detector is rearmed.
## Outputs
| Output | Function |
| --- | --- |
| `OUT0` | Selected result bit 0, least-significant bit |
| `OUT1` | Selected result bit 1 |
| `OUT2` | Selected result bit 2 |
| `OUT3` | Selected result bit 3 |
| `OUT4` | Selected result bit 4 |
| `OUT5` | Selected result bit 5, most-significant bit |
| `OUT6` | Preserved original debug trace: inverted stored numerator bit 4 |
| `OUT7` | Preserved original debug trace: inverted stored numerator bit 5 |
| Blue `BUSY` LED | Division is running |
| Green `DONE` LED | Result is ready |
| Red `DIV0` LED | Denominator was zero |
The yellow result bar graph mirrors `OUT[5:0]`. The original seven-segment display is still connected to all eight Tiny Tapeout outputs and therefore shows the raw output-bit pattern rather than a decoded decimal digit.
For division by zero, the circuit produces the defined result `Q = 0`, `R = 0`, sets `DONE = 1`, and sets `DIV0 = 1` without running the six division cycles.
## Examples
| Calculation | Quotient | Remainder |
| --- | ---: | ---: |
| `5 / 2` | 2 | 1 |
| `37 / 5` | 7 | 2 |
| `63 / 2` | 31 | 1 |
| `63 / 63` | 1 | 0 |
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2. Change input values
3. Tap to advance clock
1. Simulate with the green ▶ button
4. Watch the outputs changing
Active LOW rst
Rising Edge detector for IN6
Binary Storage
NUMERATOR
IN6: 0-Nom, 1-Denom
Binary Storage
Denominator
6-bit sequential restoring divider
Captured denominator
Control / status
7-bit partial remainder
Shared 7-bit subtract / compare stage
Result: IN6=0 quotient, IN6=1 remainder
6-bit quotient / shifting numerator
Decimal conversion: quotient / 10
Working quotient -> tens
Working remainder -> ones
10 Hz display timer: tens / ones each second
BCD to seven-segment decoder