// https://forum.arduino.cc/t/im-lost-college-project-gone-wrong/1194614
// 7seg using port addressing
// https://wokwi.com/projects/388325665223859201
void setup() {
for (int i = 2; i <= 9; i++) { // configure pins...
pinMode(i, OUTPUT); // ...as outputs
}
}
void loop() {
int analogValue = analogRead(A0); // LDR
analogValue = constrain (map (analogValue, 0, 1023, 9, -1), 0, 9); // map LDR -1 to 9 constrain 0 to 9
display (analogValue); // integer to display
}
void display(int x) { // argument is number to display
clearSegments(); // clear display
switch (x) {
case 0:setSegments(1, 1, 1, 1, 1, 1, 0, 0); break; // display "0" = 0xfd, dp = 0
case 1:setSegments(0, 1, 1, 0, 0, 0, 0, 0); break; // 1
case 2:setSegments(1, 1, 0, 1, 1, 0, 1, 0); break; // 2
case 3:setSegments(1, 1, 1, 1, 0, 0, 1, 0); break; // 3
case 4:setSegments(0, 1, 1, 0, 0, 1, 1, 0); break; // 4
case 5:setSegments(1, 0, 1, 1, 0, 1, 1, 0); break; // 5
case 6:setSegments(0, 0, 1, 1, 1, 1, 1, 0); break; // 6
case 7:setSegments(1, 1, 1, 0, 0, 0, 0, 0); break; // 7
case 8:setSegments(1, 1, 1, 1, 1, 1, 1, 0); break; // 8
case 9:setSegments(1, 1, 1, 1, 0, 1, 1, 0); break; // 9
case ('a'):
case ('A'):setSegments(1, 1, 1, 0, 1, 1, 1, 0); break;
case ('b'):
case ('B'):setSegments(0, 0, 1, 1, 1, 1, 1, 0); break;
case ('c'):
case ('C'):setSegments(0, 0, 0, 1, 1, 0, 1, 0); break;
case ('d'):
case ('D'):setSegments(0, 1, 1, 1, 1, 0, 1, 0); break;
case ('e'):
case ('E'):setSegments(1, 0, 0, 1, 1, 1, 1, 0); break;
case ('f'):
case ('F'):setSegments(1, 0, 0, 0, 1, 1, 1, 0); break;
}
}
void clearSegments() {
setSegments(0, 0, 0, 0, 0, 0, 0, 0); // a, b, c, d, e, f, g, dp
}
void setSegments(int a, int b, int c, int d, int e, int f, int g, int dp) { // arguments 0 or 1
digitalWrite(2, a); // (pin,seg)
digitalWrite(3, b);
digitalWrite(4, c);
digitalWrite(5, d);
digitalWrite(6, e);
digitalWrite(7, f);
digitalWrite(8, g);
digitalWrite(9, dp);
}
/*
setSegments
A
---
F| G |B
---
E| |C
--- o DP
D
PINS D13 D12 D11 D10 D09 D08 | D07 D06 D05 D04 D03 D02 Tx Rx | A05 A04 A03 A02 A01 A00 RST
PORT PB5 PB4 PB3 PB2 PB1 PB0 | PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 | PC5 PC4 PC3 PC2 PC1 PC0 PC6
SEGS - - - dp g f | e d c b a - - - - - - - - - -
*/